rsm.vhd

来自「用TCD1501D驱动器产生CCD驱动的6个输出信号RS、CP、SP、SH以及Φ」· VHDL 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity rsm is
    port( CLK:in std_logic;
          RS:out std_logic
         );
end entity rsm; 

architecture one of rsm is
signal CNT :integer range 0 to 7;
signal R :std_logic;
BEGIN
PROCESS(CLK,CNT)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CNT < 7 THEN
CNT <= CNT + 1 ;
ELSE CNT <= 0 ;
END IF ;
END IF ;
  CASE CNT IS
   WHEN 0 => R <='0';
  WHEN OTHERS => R <='1';
 END CASE;
END PROCESS ;
RS <= R ;
end architecture one;