shm.vhd

用TCD1501D驱动器产生CCD驱动的6个输出信号RS、CP、SP、SH以及Φ1、Φ2脉冲

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity shm is
    port( CLK,CP1:in std_logic;
          F1,F2:out std_logic;
          SH:out std_logic
         );
end entity shm; 

architecture one of shm is
signal P1:std_logic_vector(15 downto 0);
signal CP2,SH0,SH1:std_logic;


BEGIN
PROCESS(CP1,CLK)
BEGIN
IF CP1'EVENT AND CP1 ='1'THEN
CP2 <= NOT CP2 ;
END IF ;
F1 <= (NOT CP2) OR SH1 ;
F2 <= CP2 AND (NOT SH1) ;

IF CLK'EVENT AND CLK='1'THEN
IF P1 < "1010001010000000" THEN
IF P1 <= 4 THEN
SH0 <='0';
SH1 <='0';
ELSIF (P1 > 7 AND P1 <= 15) THEN
SH0 <='1';
SH1 <='1';
ELSIF (P1 > 4 AND P1 <= 7) OR( P1 > 15 AND P1 <=18) THEN
SH0 <='0';
SH1 <='1';
ELSE SH0 <='0';
SH1 <='0';
END IF ;
P1 <= P1+1 ;
ELSE
P1 <= "0000000000000000" ;
END IF ;
END IF ;
END PROCESS ;
SH <= SH0 ;
end architecture one;