fpq.vhd

来自「用TCD1501D驱动器产生CCD驱动的6个输出信号RS、CP、SP、SH以及Φ」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;


entity fpq is
    port( CLK:in std_logic;
          CLK_OUT:out std_logic
         );
end entity fpq; 

architecture one of fpq is
signal CNT:std_logic_vector(2 downto 0);

BEGIN
PROCESS(CLK)
 BEGIN
  IF CLK'EVENT AND CLK='1' THEN
    if(CNT<7)then
        CNT<=CNT+1;
        CLK_OUT<='0';
    else 
        CNT<=(others=>'0');
        CLK_OUT<='1';

  END IF;
  END IF;
 END PROCESS;
END ONE;