📄 yima.tan.rpt
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Classic Timing Analyzer report for YIMA
Thu Nov 27 18:17:24 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. tpd
5. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
; Worst-case tpd ; N/A ; None ; 11.472 ns ; a[2] ; y[0] ; -- ; -- ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+------+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5Q208C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+-----------------------------------------------------------+
; tpd ;
+-------+-------------------+-----------------+------+------+
; Slack ; Required P2P Time ; Actual P2P Time ; From ; To ;
+-------+-------------------+-----------------+------+------+
; N/A ; None ; 11.472 ns ; a[2] ; y[0] ;
; N/A ; None ; 11.456 ns ; a[2] ; y[7] ;
; N/A ; None ; 11.402 ns ; a[0] ; y[0] ;
; N/A ; None ; 11.363 ns ; a[2] ; y[2] ;
; N/A ; None ; 11.331 ns ; a[0] ; y[7] ;
; N/A ; None ; 11.330 ns ; a[0] ; y[2] ;
; N/A ; None ; 11.235 ns ; a[2] ; y[3] ;
; N/A ; None ; 11.211 ns ; a[1] ; y[0] ;
; N/A ; None ; 11.184 ns ; a[0] ; y[3] ;
; N/A ; None ; 11.143 ns ; a[1] ; y[2] ;
; N/A ; None ; 11.141 ns ; a[1] ; y[7] ;
; N/A ; None ; 11.089 ns ; a[2] ; y[5] ;
; N/A ; None ; 11.073 ns ; a[2] ; y[4] ;
; N/A ; None ; 11.035 ns ; a[2] ; y[6] ;
; N/A ; None ; 11.022 ns ; a[2] ; y[1] ;
; N/A ; None ; 10.992 ns ; a[1] ; y[3] ;
; N/A ; None ; 10.942 ns ; a[0] ; y[1] ;
; N/A ; None ; 10.934 ns ; a[0] ; y[5] ;
; N/A ; None ; 10.922 ns ; a[0] ; y[6] ;
; N/A ; None ; 10.904 ns ; a[0] ; y[4] ;
; N/A ; None ; 10.749 ns ; a[1] ; y[1] ;
; N/A ; None ; 10.742 ns ; a[1] ; y[5] ;
; N/A ; None ; 10.733 ns ; a[1] ; y[6] ;
; N/A ; None ; 10.712 ns ; a[1] ; y[4] ;
+-------+-------------------+-----------------+------+------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Thu Nov 27 18:17:23 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off YIMA -c YIMA --timing_analysis_only
Info: Longest tpd from source pin "a[2]" to destination pin "y[0]" is 11.472 ns
Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_34; Fanout = 8; PIN Node = 'a[2]'
Info: 2: + IC(5.738 ns) + CELL(0.539 ns) = 7.262 ns; Loc. = LCCOMB_X1_Y3_N16; Fanout = 1; COMB Node = 'Mux7~80'
Info: 3: + IC(0.930 ns) + CELL(3.280 ns) = 11.472 ns; Loc. = PIN_47; Fanout = 0; PIN Node = 'y[0]'
Info: Total cell delay = 4.804 ns ( 41.88 % )
Info: Total interconnect delay = 6.668 ns ( 58.12 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings
Info: Allocated 115 megabytes of memory during processing
Info: Processing ended: Thu Nov 27 18:17:24 2008
Info: Elapsed time: 00:00:01
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