prev_cmp_tm.tan.qmsg

基于fpga数字钟系统

{ "Info" "ITDB_TSU_RESULT" "clock:inst\|mhour22\[0\] K1 CLK 3.547 ns register " "Info: tsu for register \"clock:inst\|mhour22\[0\]\" (data pin = \"K1\", clock pin = \"CLK\") is 3.547 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.095 ns + Longest pin register " "Info: + Longest pin to register delay is 11.095 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns K1 1 PIN PIN_99 18 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_99; Fanout = 18; PIN Node = 'K1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { K1 } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 160 -16 152 176 "K1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.620 ns) + CELL(0.370 ns) 7.974 ns K0~19 2 COMB LCCOMB_X24_Y8_N0 6 " "Info: 2: + IC(6.620 ns) + CELL(0.370 ns) = 7.974 ns; Loc. = LCCOMB_X24_Y8_N0; Fanout = 6; COMB Node = 'K0~19'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.990 ns" { K1 K0~19 } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 128 -16 152 144 "K0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.707 ns) + CELL(0.651 ns) 9.332 ns clock:inst\|mhour11\[3\]~547 3 COMB LCCOMB_X25_Y8_N28 4 " "Info: 3: + IC(0.707 ns) + CELL(0.651 ns) = 9.332 ns; Loc. = LCCOMB_X25_Y8_N28; Fanout = 4; COMB Node = 'clock:inst\|mhour11\[3\]~547'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.358 ns" { K0~19 clock:inst|mhour11[3]~547 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.378 ns) + CELL(0.206 ns) 9.916 ns clock:inst\|mhour22\[2\]~566 4 COMB LCCOMB_X25_Y8_N14 4 " "Info: 4: + IC(0.378 ns) + CELL(0.206 ns) = 9.916 ns; Loc. = LCCOMB_X25_Y8_N14; Fanout = 4; COMB Node = 'clock:inst\|mhour22\[2\]~566'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.584 ns" { clock:inst|mhour11[3]~547 clock:inst|mhour22[2]~566 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.324 ns) + CELL(0.855 ns) 11.095 ns clock:inst\|mhour22\[0\] 5 REG LCFF_X25_Y8_N21 4 " "Info: 5: + IC(0.324 ns) + CELL(0.855 ns) = 11.095 ns; Loc. = LCFF_X25_Y8_N21; Fanout = 4; REG Node = 'clock:inst\|mhour22\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.179 ns" { clock:inst|mhour22[2]~566 clock:inst|mhour22[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.066 ns ( 27.63 % ) " "Info: Total cell delay = 3.066 ns ( 27.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.029 ns ( 72.37 % ) " "Info: Total interconnect delay = 8.029 ns ( 72.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.095 ns" { K1 K0~19 clock:inst|mhour11[3]~547 clock:inst|mhour22[2]~566 clock:inst|mhour22[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.095 ns" { K1 {} K1~combout {} K0~19 {} clock:inst|mhour11[3]~547 {} clock:inst|mhour22[2]~566 {} clock:inst|mhour22[0] {} } { 0.000ns 0.000ns 6.620ns 0.707ns 0.378ns 0.324ns } { 0.000ns 0.984ns 0.370ns 0.651ns 0.206ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.508 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 7.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.677 ns) + CELL(0.970 ns) 3.787 ns FPQ:inst6\|QD 2 REG LCFF_X14_Y7_N25 1 " "Info: 2: + IC(1.677 ns) + CELL(0.970 ns) = 3.787 ns; Loc. = LCFF_X14_Y7_N25; Fanout = 1; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.647 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.209 ns) + CELL(0.000 ns) 5.996 ns FPQ:inst6\|QD~clkctrl 3 COMB CLKCTRL_G7 24 " "Info: 3: + IC(2.209 ns) + CELL(0.000 ns) = 5.996 ns; Loc. = CLKCTRL_G7; Fanout = 24; COMB Node = 'FPQ:inst6\|QD~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.209 ns" { FPQ:inst6|QD FPQ:inst6|QD~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.846 ns) + CELL(0.666 ns) 7.508 ns clock:inst\|mhour22\[0\] 4 REG LCFF_X25_Y8_N21 4 " "Info: 4: + IC(0.846 ns) + CELL(0.666 ns) = 7.508 ns; Loc. = LCFF_X25_Y8_N21; Fanout = 4; REG Node = 'clock:inst\|mhour22\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.512 ns" { FPQ:inst6|QD~clkctrl clock:inst|mhour22[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 36.97 % ) " "Info: Total cell delay = 2.776 ns ( 36.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.732 ns ( 63.03 % ) " "Info: Total interconnect delay = 4.732 ns ( 63.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.508 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mhour22[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.508 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mhour22[0] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.095 ns" { K1 K0~19 clock:inst|mhour11[3]~547 clock:inst|mhour22[2]~566 clock:inst|mhour22[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.095 ns" { K1 {} K1~combout {} K0~19 {} clock:inst|mhour11[3]~547 {} clock:inst|mhour22[2]~566 {} clock:inst|mhour22[0] {} } { 0.000ns 0.000ns 6.620ns 0.707ns 0.378ns 0.324ns } { 0.000ns 0.984ns 0.370ns 0.651ns 0.206ns 0.855ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.508 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mhour22[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.508 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mhour22[0] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK led\[1\] seltime:inst2\|daout\[2\] 15.492 ns register " "Info: tco from clock \"CLK\" to destination pin \"led\[1\]\" through register \"seltime:inst2\|daout\[2\]\" is 15.492 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 9.234 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 9.234 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.513 ns) + CELL(0.970 ns) 3.623 ns FPQ:inst6\|QG 2 REG LCFF_X25_Y6_N1 3 " "Info: 2: + IC(1.513 ns) + CELL(0.970 ns) = 3.623 ns; Loc. = LCFF_X25_Y6_N1; Fanout = 3; REG Node = 'FPQ:inst6\|QG'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { CLK FPQ:inst6|QG } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.970 ns) 4.980 ns seltime:inst2\|count\[1\] 3 REG LCFF_X25_Y6_N9 19 " "Info: 3: + IC(0.387 ns) + CELL(0.970 ns) = 4.980 ns; Loc. = LCFF_X25_Y6_N9; Fanout = 19; REG Node = 'seltime:inst2\|count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.357 ns" { FPQ:inst6|QG seltime:inst2|count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.506 ns) + CELL(0.624 ns) 6.110 ns seltime:inst2\|Mux1~19 4 COMB LCCOMB_X25_Y6_N4 1 " "Info: 4: + IC(0.506 ns) + CELL(0.624 ns) = 6.110 ns; Loc. = LCCOMB_X25_Y6_N4; Fanout = 1; COMB Node = 'seltime:inst2\|Mux1~19'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.130 ns" { seltime:inst2|count[1] seltime:inst2|Mux1~19 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.524 ns) + CELL(0.000 ns) 7.634 ns seltime:inst2\|Mux1~19clkctrl 5 COMB CLKCTRL_G6 5 " "Info: 5: + IC(1.524 ns) + CELL(0.000 ns) = 7.634 ns; Loc. = CLKCTRL_G6; Fanout = 5; COMB Node = 'seltime:inst2\|Mux1~19clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.394 ns) + CELL(0.206 ns) 9.234 ns seltime:inst2\|daout\[2\] 6 REG LCCOMB_X26_Y6_N12 7 " "Info: 6: + IC(1.394 ns) + CELL(0.206 ns) = 9.234 ns; Loc. = LCCOMB_X26_Y6_N12; Fanout = 7; REG Node = 'seltime:inst2\|daout\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { seltime:inst2|Mux1~19clkctrl seltime:inst2|daout[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.910 ns ( 42.34 % ) " "Info: Total cell delay = 3.910 ns ( 42.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.324 ns ( 57.66 % ) " "Info: Total interconnect delay = 5.324 ns ( 57.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.234 ns" { CLK FPQ:inst6|QG seltime:inst2|count[1] seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl seltime:inst2|daout[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.234 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[1] {} seltime:inst2|Mux1~19 {} seltime:inst2|Mux1~19clkctrl {} seltime:inst2|daout[2] {} } { 0.000ns 0.000ns 1.513ns 0.387ns 0.506ns 1.524ns 1.394ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.258 ns + Longest register pin " "Info: + Longest register to pin delay is 6.258 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seltime:inst2\|daout\[2\] 1 REG LCCOMB_X26_Y6_N12 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X26_Y6_N12; Fanout = 7; REG Node = 'seltime:inst2\|daout\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { seltime:inst2|daout[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.140 ns) + CELL(0.650 ns) 1.790 ns deled:inst4\|led\[1\]~724 2 COMB LCCOMB_X26_Y6_N16 1 " "Info: 2: + IC(1.140 ns) + CELL(0.650 ns) = 1.790 ns; Loc. = LCCOMB_X26_Y6_N16; Fanout = 1; COMB Node = 'deled:inst4\|led\[1\]~724'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.790 ns" { seltime:inst2|daout[2] deled:inst4|led[1]~724 } "NODE_NAME" } } { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.372 ns) + CELL(3.096 ns) 6.258 ns led\[1\] 3 PIN PIN_134 0 " "Info: 3: + IC(1.372 ns) + CELL(3.096 ns) = 6.258 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'led\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.468 ns" { deled:inst4|led[1]~724 led[1] } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 72 1040 1216 88 "led\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.746 ns ( 59.86 % ) " "Info: Total cell delay = 3.746 ns ( 59.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.512 ns ( 40.14 % ) " "Info: Total interconnect delay = 2.512 ns ( 40.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.258 ns" { seltime:inst2|daout[2] deled:inst4|led[1]~724 led[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.258 ns" { seltime:inst2|daout[2] {} deled:inst4|led[1]~724 {} led[1] {} } { 0.000ns 1.140ns 1.372ns } { 0.000ns 0.650ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.234 ns" { CLK FPQ:inst6|QG seltime:inst2|count[1] seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl seltime:inst2|daout[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.234 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[1] {} seltime:inst2|Mux1~19 {} seltime:inst2|Mux1~19clkctrl {} seltime:inst2|daout[2] {} } { 0.000ns 0.000ns 1.513ns 0.387ns 0.506ns 1.524ns 1.394ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.258 ns" { seltime:inst2|daout[2] deled:inst4|led[1]~724 led[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.258 ns" { seltime:inst2|daout[2] {} deled:inst4|led[1]~724 {} led[1] {} } { 0.000ns 1.140ns 1.372ns } { 0.000ns 0.650ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "clock:inst\|mhour11\[0\] K0 CLK 0.246 ns register " "Info: th for register \"clock:inst\|mhour11\[0\]\" (data pin = \"K0\", clock pin = \"CLK\") is 0.246 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.495 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 7.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.677 ns) + CELL(0.970 ns) 3.787 ns FPQ:inst6\|QD 2 REG LCFF_X14_Y7_N25 1 " "Info: 2: + IC(1.677 ns) + CELL(0.970 ns) = 3.787 ns; Loc. = LCFF_X14_Y7_N25; Fanout = 1; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.647 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.209 ns) + CELL(0.000 ns) 5.996 ns FPQ:inst6\|QD~clkctrl 3 COMB CLKCTRL_G7 24 " "Info: 3: + IC(2.209 ns) + CELL(0.000 ns) = 5.996 ns; Loc. = CLKCTRL_G7; Fanout = 24; COMB Node = 'FPQ:inst6\|QD~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.209 ns" { FPQ:inst6|QD FPQ:inst6|QD~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 7.495 ns clock:inst\|mhour11\[0\] 4 REG LCFF_X25_Y7_N13 8 " "Info: 4: + IC(0.833 ns) + CELL(0.666 ns) = 7.495 ns; Loc. = LCFF_X25_Y7_N13; Fanout = 8; REG Node = 'clock:inst\|mhour11\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { FPQ:inst6|QD~clkctrl clock:inst|mhour11[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 37.04 % ) " "Info: Total cell delay = 2.776 ns ( 37.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.719 ns ( 62.96 % ) " "Info: Total interconnect delay = 4.719 ns ( 62.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mhour11[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mhour11[0] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.833ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.555 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.555 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns K0 1 PIN PIN_97 14 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 14; PIN Node = 'K0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { K0 } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 128 -16 152 144 "K0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.247 ns) + CELL(0.206 ns) 7.447 ns clock:inst\|mhour11~552 2 COMB LCCOMB_X25_Y7_N12 1 " "Info: 2: + IC(6.247 ns) + CELL(0.206 ns) = 7.447 ns; Loc. = LCCOMB_X25_Y7_N12; Fanout = 1; COMB Node = 'clock:inst\|mhour11~552'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.453 ns" { K0 clock:inst|mhour11~552 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.555 ns clock:inst\|mhour11\[0\] 3 REG LCFF_X25_Y7_N13 8 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 7.555 ns; Loc. = LCFF_X25_Y7_N13; Fanout = 8; REG Node = 'clock:inst\|mhour11\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { clock:inst|mhour11~552 clock:inst|mhour11[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.308 ns ( 17.31 % ) " "Info: Total cell delay = 1.308 ns ( 17.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.247 ns ( 82.69 % ) " "Info: Total interconnect delay = 6.247 ns ( 82.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.555 ns" { K0 clock:inst|mhour11~552 clock:inst|mhour11[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.555 ns" { K0 {} K0~combout {} clock:inst|mhour11~552 {} clock:inst|mhour11[0] {} } { 0.000ns 0.000ns 6.247ns 0.000ns } { 0.000ns 0.994ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mhour11[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mhour11[0] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.833ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.555 ns" { K0 clock:inst|mhour11~552 clock:inst|mhour11[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.555 ns" { K0 {} K0~combout {} clock:inst|mhour11~552 {} clock:inst|mhour11[0] {} } { 0.000ns 0.000ns 6.247ns 0.000ns } { 0.000ns 0.994ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}