prev_cmp_tm.tan.qmsg

基于fpga数字钟系统

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register clock:inst\|msecond1\[2\] register clock:inst\|mminite2\[2\] 182.58 MHz 5.477 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 182.58 MHz between source register \"clock:inst\|msecond1\[2\]\" and destination register \"clock:inst\|mminite2\[2\]\" (period= 5.477 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.226 ns + Longest register register " "Info: + Longest register to register delay is 5.226 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|msecond1\[2\] 1 REG LCFF_X25_Y7_N17 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y7_N17; Fanout = 4; REG Node = 'clock:inst\|msecond1\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|msecond1[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.173 ns) + CELL(0.651 ns) 1.824 ns clock:inst\|Equal0~58 2 COMB LCCOMB_X25_Y8_N6 5 " "Info: 2: + IC(1.173 ns) + CELL(0.651 ns) = 1.824 ns; Loc. = LCCOMB_X25_Y8_N6; Fanout = 5; COMB Node = 'clock:inst\|Equal0~58'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.824 ns" { clock:inst|msecond1[2] clock:inst|Equal0~58 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.386 ns) + CELL(0.202 ns) 2.412 ns clock:inst\|mminite1\[0\]~500 3 COMB LCCOMB_X25_Y8_N0 1 " "Info: 3: + IC(0.386 ns) + CELL(0.202 ns) = 2.412 ns; Loc. = LCCOMB_X25_Y8_N0; Fanout = 1; COMB Node = 'clock:inst\|mminite1\[0\]~500'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.588 ns" { clock:inst|Equal0~58 clock:inst|mminite1[0]~500 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.206 ns) 2.988 ns clock:inst\|mminite1\[0\]~501 4 COMB LCCOMB_X25_Y8_N8 5 " "Info: 4: + IC(0.370 ns) + CELL(0.206 ns) = 2.988 ns; Loc. = LCCOMB_X25_Y8_N8; Fanout = 5; COMB Node = 'clock:inst\|mminite1\[0\]~501'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.576 ns" { clock:inst|mminite1[0]~500 clock:inst|mminite1[0]~501 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.370 ns) 3.741 ns clock:inst\|mminite2\[3\]~594 5 COMB LCCOMB_X25_Y8_N2 4 " "Info: 5: + IC(0.383 ns) + CELL(0.370 ns) = 3.741 ns; Loc. = LCCOMB_X25_Y8_N2; Fanout = 4; COMB Node = 'clock:inst\|mminite2\[3\]~594'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.753 ns" { clock:inst|mminite1[0]~501 clock:inst|mminite2[3]~594 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.630 ns) + CELL(0.855 ns) 5.226 ns clock:inst\|mminite2\[2\] 6 REG LCFF_X24_Y8_N15 4 " "Info: 6: + IC(0.630 ns) + CELL(0.855 ns) = 5.226 ns; Loc. = LCFF_X24_Y8_N15; Fanout = 4; REG Node = 'clock:inst\|mminite2\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.485 ns" { clock:inst|mminite2[3]~594 clock:inst|mminite2[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.284 ns ( 43.70 % ) " "Info: Total cell delay = 2.284 ns ( 43.70 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.942 ns ( 56.30 % ) " "Info: Total interconnect delay = 2.942 ns ( 56.30 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.226 ns" { clock:inst|msecond1[2] clock:inst|Equal0~58 clock:inst|mminite1[0]~500 clock:inst|mminite1[0]~501 clock:inst|mminite2[3]~594 clock:inst|mminite2[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.226 ns" { clock:inst|msecond1[2] {} clock:inst|Equal0~58 {} clock:inst|mminite1[0]~500 {} clock:inst|mminite1[0]~501 {} clock:inst|mminite2[3]~594 {} clock:inst|mminite2[2] {} } { 0.000ns 1.173ns 0.386ns 0.370ns 0.383ns 0.630ns } { 0.000ns 0.651ns 0.202ns 0.206ns 0.370ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.013 ns - Smallest " "Info: - Smallest clock skew is 0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 7.508 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 7.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.677 ns) + CELL(0.970 ns) 3.787 ns FPQ:inst6\|QD 2 REG LCFF_X14_Y7_N25 1 " "Info: 2: + IC(1.677 ns) + CELL(0.970 ns) = 3.787 ns; Loc. = LCFF_X14_Y7_N25; Fanout = 1; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.647 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.209 ns) + CELL(0.000 ns) 5.996 ns FPQ:inst6\|QD~clkctrl 3 COMB CLKCTRL_G7 24 " "Info: 3: + IC(2.209 ns) + CELL(0.000 ns) = 5.996 ns; Loc. = CLKCTRL_G7; Fanout = 24; COMB Node = 'FPQ:inst6\|QD~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.209 ns" { FPQ:inst6|QD FPQ:inst6|QD~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.846 ns) + CELL(0.666 ns) 7.508 ns clock:inst\|mminite2\[2\] 4 REG LCFF_X24_Y8_N15 4 " "Info: 4: + IC(0.846 ns) + CELL(0.666 ns) = 7.508 ns; Loc. = LCFF_X24_Y8_N15; Fanout = 4; REG Node = 'clock:inst\|mminite2\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.512 ns" { FPQ:inst6|QD~clkctrl clock:inst|mminite2[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 36.97 % ) " "Info: Total cell delay = 2.776 ns ( 36.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.732 ns ( 63.03 % ) " "Info: Total interconnect delay = 4.732 ns ( 63.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.508 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mminite2[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.508 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mminite2[2] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 7.495 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 7.495 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.677 ns) + CELL(0.970 ns) 3.787 ns FPQ:inst6\|QD 2 REG LCFF_X14_Y7_N25 1 " "Info: 2: + IC(1.677 ns) + CELL(0.970 ns) = 3.787 ns; Loc. = LCFF_X14_Y7_N25; Fanout = 1; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.647 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.209 ns) + CELL(0.000 ns) 5.996 ns FPQ:inst6\|QD~clkctrl 3 COMB CLKCTRL_G7 24 " "Info: 3: + IC(2.209 ns) + CELL(0.000 ns) = 5.996 ns; Loc. = CLKCTRL_G7; Fanout = 24; COMB Node = 'FPQ:inst6\|QD~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.209 ns" { FPQ:inst6|QD FPQ:inst6|QD~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.666 ns) 7.495 ns clock:inst\|msecond1\[2\] 4 REG LCFF_X25_Y7_N17 4 " "Info: 4: + IC(0.833 ns) + CELL(0.666 ns) = 7.495 ns; Loc. = LCFF_X25_Y7_N17; Fanout = 4; REG Node = 'clock:inst\|msecond1\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.499 ns" { FPQ:inst6|QD~clkctrl clock:inst|msecond1[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 37.04 % ) " "Info: Total cell delay = 2.776 ns ( 37.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.719 ns ( 62.96 % ) " "Info: Total interconnect delay = 4.719 ns ( 62.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|msecond1[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|msecond1[2] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.833ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.508 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mminite2[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.508 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mminite2[2] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|msecond1[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|msecond1[2] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.833ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.226 ns" { clock:inst|msecond1[2] clock:inst|Equal0~58 clock:inst|mminite1[0]~500 clock:inst|mminite1[0]~501 clock:inst|mminite2[3]~594 clock:inst|mminite2[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.226 ns" { clock:inst|msecond1[2] {} clock:inst|Equal0~58 {} clock:inst|mminite1[0]~500 {} clock:inst|mminite1[0]~501 {} clock:inst|mminite2[3]~594 {} clock:inst|mminite2[2] {} } { 0.000ns 1.173ns 0.386ns 0.370ns 0.383ns 0.630ns } { 0.000ns 0.651ns 0.202ns 0.206ns 0.370ns 0.855ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.508 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mminite2[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.508 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mminite2[2] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.846ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.495 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|msecond1[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.495 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|msecond1[2] {} } { 0.000ns 0.000ns 1.677ns 2.209ns 0.833ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 13 " "Warning: Circuit may not operate. Detected 13 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "seltime:inst2\|count\[2\] seltime:inst2\|dp CLK 1.899 ns " "Info: Found hold time violation between source  pin or register \"seltime:inst2\|count\[2\]\" and destination pin or register \"seltime:inst2\|dp\" for clock \"CLK\" (Hold time is 1.899 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.472 ns + Largest " "Info: + Largest clock skew is 4.472 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 9.148 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 9.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.513 ns) + CELL(0.970 ns) 3.623 ns FPQ:inst6\|QG 2 REG LCFF_X25_Y6_N1 3 " "Info: 2: + IC(1.513 ns) + CELL(0.970 ns) = 3.623 ns; Loc. = LCFF_X25_Y6_N1; Fanout = 3; REG Node = 'FPQ:inst6\|QG'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { CLK FPQ:inst6|QG } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.970 ns) 4.980 ns seltime:inst2\|count\[1\] 3 REG LCFF_X25_Y6_N9 19 " "Info: 3: + IC(0.387 ns) + CELL(0.970 ns) = 4.980 ns; Loc. = LCFF_X25_Y6_N9; Fanout = 19; REG Node = 'seltime:inst2\|count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.357 ns" { FPQ:inst6|QG seltime:inst2|count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.506 ns) + CELL(0.624 ns) 6.110 ns seltime:inst2\|Mux1~19 4 COMB LCCOMB_X25_Y6_N4 1 " "Info: 4: + IC(0.506 ns) + CELL(0.624 ns) = 6.110 ns; Loc. = LCCOMB_X25_Y6_N4; Fanout = 1; COMB Node = 'seltime:inst2\|Mux1~19'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.130 ns" { seltime:inst2|count[1] seltime:inst2|Mux1~19 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.524 ns) + CELL(0.000 ns) 7.634 ns seltime:inst2\|Mux1~19clkctrl 5 COMB CLKCTRL_G6 5 " "Info: 5: + IC(1.524 ns) + CELL(0.000 ns) = 7.634 ns; Loc. = CLKCTRL_G6; Fanout = 5; COMB Node = 'seltime:inst2\|Mux1~19clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.524 ns" { seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.308 ns) + CELL(0.206 ns) 9.148 ns seltime:inst2\|dp 6 REG LCCOMB_X27_Y6_N10 1 " "Info: 6: + IC(1.308 ns) + CELL(0.206 ns) = 9.148 ns; Loc. = LCCOMB_X27_Y6_N10; Fanout = 1; REG Node = 'seltime:inst2\|dp'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.514 ns" { seltime:inst2|Mux1~19clkctrl seltime:inst2|dp } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.910 ns ( 42.74 % ) " "Info: Total cell delay = 3.910 ns ( 42.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.238 ns ( 57.26 % ) " "Info: Total interconnect delay = 5.238 ns ( 57.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.148 ns" { CLK FPQ:inst6|QG seltime:inst2|count[1] seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl seltime:inst2|dp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.148 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[1] {} seltime:inst2|Mux1~19 {} seltime:inst2|Mux1~19clkctrl {} seltime:inst2|dp {} } { 0.000ns 0.000ns 1.513ns 0.387ns 0.506ns 1.524ns 1.308ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 4.676 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 4.676 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.513 ns) + CELL(0.970 ns) 3.623 ns FPQ:inst6\|QG 2 REG LCFF_X25_Y6_N1 3 " "Info: 2: + IC(1.513 ns) + CELL(0.970 ns) = 3.623 ns; Loc. = LCFF_X25_Y6_N1; Fanout = 3; REG Node = 'FPQ:inst6\|QG'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { CLK FPQ:inst6|QG } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.666 ns) 4.676 ns seltime:inst2\|count\[2\] 3 REG LCFF_X25_Y6_N15 18 " "Info: 3: + IC(0.387 ns) + CELL(0.666 ns) = 4.676 ns; Loc. = LCFF_X25_Y6_N15; Fanout = 18; REG Node = 'seltime:inst2\|count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.053 ns" { FPQ:inst6|QG seltime:inst2|count[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 59.37 % ) " "Info: Total cell delay = 2.776 ns ( 59.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 40.63 % ) " "Info: Total interconnect delay = 1.900 ns ( 40.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.676 ns" { CLK FPQ:inst6|QG seltime:inst2|count[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.676 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[2] {} } { 0.000ns 0.000ns 1.513ns 0.387ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.148 ns" { CLK FPQ:inst6|QG seltime:inst2|count[1] seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl seltime:inst2|dp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.148 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[1] {} seltime:inst2|Mux1~19 {} seltime:inst2|Mux1~19clkctrl {} seltime:inst2|dp {} } { 0.000ns 0.000ns 1.513ns 0.387ns 0.506ns 1.524ns 1.308ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.676 ns" { CLK FPQ:inst6|QG seltime:inst2|count[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.676 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[2] {} } { 0.000ns 0.000ns 1.513ns 0.387ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.269 ns - Shortest register register " "Info: - Shortest register to register delay is 2.269 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seltime:inst2\|count\[2\] 1 REG LCFF_X25_Y6_N15 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y6_N15; Fanout = 18; REG Node = 'seltime:inst2\|count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { seltime:inst2|count[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.534 ns) + CELL(0.370 ns) 0.904 ns seltime:inst2\|Mux0~25 2 COMB LCCOMB_X25_Y6_N24 1 " "Info: 2: + IC(0.534 ns) + CELL(0.370 ns) = 0.904 ns; Loc. = LCCOMB_X25_Y6_N24; Fanout = 1; COMB Node = 'seltime:inst2\|Mux0~25'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.904 ns" { seltime:inst2|count[2] seltime:inst2|Mux0~25 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.995 ns) + CELL(0.370 ns) 2.269 ns seltime:inst2\|dp 3 REG LCCOMB_X27_Y6_N10 1 " "Info: 3: + IC(0.995 ns) + CELL(0.370 ns) = 2.269 ns; Loc. = LCCOMB_X27_Y6_N10; Fanout = 1; REG Node = 'seltime:inst2\|dp'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.365 ns" { seltime:inst2|Mux0~25 seltime:inst2|dp } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.740 ns ( 32.61 % ) " "Info: Total cell delay = 0.740 ns ( 32.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.529 ns ( 67.39 % ) " "Info: Total interconnect delay = 1.529 ns ( 67.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.269 ns" { seltime:inst2|count[2] seltime:inst2|Mux0~25 seltime:inst2|dp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.269 ns" { seltime:inst2|count[2] {} seltime:inst2|Mux0~25 {} seltime:inst2|dp {} } { 0.000ns 0.534ns 0.995ns } { 0.000ns 0.370ns 0.370ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 10 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.148 ns" { CLK FPQ:inst6|QG seltime:inst2|count[1] seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl seltime:inst2|dp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.148 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[1] {} seltime:inst2|Mux1~19 {} seltime:inst2|Mux1~19clkctrl {} seltime:inst2|dp {} } { 0.000ns 0.000ns 1.513ns 0.387ns 0.506ns 1.524ns 1.308ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.676 ns" { CLK FPQ:inst6|QG seltime:inst2|count[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.676 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[2] {} } { 0.000ns 0.000ns 1.513ns 0.387ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.269 ns" { seltime:inst2|count[2] seltime:inst2|Mux0~25 seltime:inst2|dp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.269 ns" { seltime:inst2|count[2] {} seltime:inst2|Mux0~25 {} seltime:inst2|dp {} } { 0.000ns 0.534ns 0.995ns } { 0.000ns 0.370ns 0.370ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}