prev_cmp_tm.tan.qmsg

基于fpga数字钟系统

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "seltime:inst2\|daout\[2\] " "Warning: Node \"seltime:inst2\|daout\[2\]\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seltime:inst2\|daout\[3\] " "Warning: Node \"seltime:inst2\|daout\[3\]\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seltime:inst2\|daout\[0\] " "Warning: Node \"seltime:inst2\|daout\[0\]\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seltime:inst2\|daout\[1\] " "Warning: Node \"seltime:inst2\|daout\[1\]\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "seltime:inst2\|dp " "Warning: Node \"seltime:inst2\|dp\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 10 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK " "Info: Assuming node \"CLK\" is an undefined clock" {  } { { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLK" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "seltime:inst2\|Mux1~19 " "Info: Detected gated clock \"seltime:inst2\|Mux1~19\" as buffer" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "seltime:inst2\|Mux1~19" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "FPQ:inst6\|QD " "Info: Detected ripple clock \"FPQ:inst6\|QD\" as buffer" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FPQ:inst6\|QD" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "seltime:inst2\|count\[2\] " "Info: Detected ripple clock \"seltime:inst2\|count\[2\]\" as buffer" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "seltime:inst2\|count\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "FPQ:inst6\|QG " "Info: Detected ripple clock \"FPQ:inst6\|QG\" as buffer" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "FPQ:inst6\|QG" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "seltime:inst2\|count\[1\] " "Info: Detected ripple clock \"seltime:inst2\|count\[1\]\" as buffer" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "seltime:inst2\|count\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}