prev_cmp_clock.qmsg

基于fpga数字钟系统

{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 6 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "176 " "Info: Allocated 176 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 16:20:29 2008 " "Info: Processing ended: Fri Nov 28 16:20:29 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 28 16:20:29 2008 " "Info: Processing started: Fri Nov 28 16:20:29 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off clock -c clock " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off clock -c clock" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 16:20:32 2008 " "Info: Processing ended: Fri Nov 28 16:20:32 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 28 16:20:32 2008 " "Info: Processing started: Fri Nov 28 16:20:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 5 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register msecond1\[1\] register mhour22\[1\] 185.8 MHz 5.382 ns Internal " "Info: Clock \"clk\" has Internal fmax of 185.8 MHz between source register \"msecond1\[1\]\" and destination register \"mhour22\[1\]\" (period= 5.382 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.115 ns + Longest register register " "Info: + Longest register to register delay is 5.115 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns msecond1\[1\] 1 REG LCFF_X9_Y6_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X9_Y6_N9; Fanout = 5; REG Node = 'msecond1\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { msecond1[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.793 ns) + CELL(0.651 ns) 1.444 ns Equal0~52 2 COMB LCCOMB_X9_Y6_N20 5 " "Info: 2: + IC(0.793 ns) + CELL(0.651 ns) = 1.444 ns; Loc. = LCCOMB_X9_Y6_N20; Fanout = 5; COMB Node = 'Equal0~52'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.444 ns" { msecond1[1] Equal0~52 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.651 ns) 2.506 ns mhour11\[0\]~500 3 COMB LCCOMB_X9_Y6_N4 3 " "Info: 3: + IC(0.411 ns) + CELL(0.651 ns) = 2.506 ns; Loc. = LCCOMB_X9_Y6_N4; Fanout = 3; COMB Node = 'mhour11\[0\]~500'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.062 ns" { Equal0~52 mhour11[0]~500 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.695 ns) + CELL(0.206 ns) 3.407 ns mhour22~687 4 COMB LCCOMB_X9_Y6_N10 2 " "Info: 4: + IC(0.695 ns) + CELL(0.206 ns) = 3.407 ns; Loc. = LCCOMB_X9_Y6_N10; Fanout = 2; COMB Node = 'mhour22~687'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.901 ns" { mhour11[0]~500 mhour22~687 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.011 ns) + CELL(0.589 ns) 5.007 ns mhour22~689 5 COMB LCCOMB_X7_Y6_N10 1 " "Info: 5: + IC(1.011 ns) + CELL(0.589 ns) = 5.007 ns; Loc. = LCCOMB_X7_Y6_N10; Fanout = 1; COMB Node = 'mhour22~689'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { mhour22~687 mhour22~689 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.115 ns mhour22\[1\] 6 REG LCFF_X7_Y6_N11 4 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 5.115