tm.tan.qmsg

基于fpga数字钟系统

{ "Info" "ITDB_TSU_RESULT" "clock:inst\|mhour22\[0\] K0 CLK 5.379 ns register " "Info: tsu for register \"clock:inst\|mhour22\[0\]\" (data pin = \"K0\", clock pin = \"CLK\") is 5.379 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.123 ns + Longest pin register " "Info: + Longest pin to register delay is 12.123 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.994 ns) 0.994 ns K0 1 PIN PIN_97 14 " "Info: 1: + IC(0.000 ns) + CELL(0.994 ns) = 0.994 ns; Loc. = PIN_97; Fanout = 14; PIN Node = 'K0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { K0 } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 128 -16 152 144 "K0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.111 ns) + CELL(0.370 ns) 8.475 ns K0~19 2 COMB LCCOMB_X22_Y8_N30 6 " "Info: 2: + IC(7.111 ns) + CELL(0.370 ns) = 8.475 ns; Loc. = LCCOMB_X22_Y8_N30; Fanout = 6; COMB Node = 'K0~19'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.481 ns" { K0 K0~19 } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 128 -16 152 144 "K0" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.098 ns) + CELL(0.624 ns) 10.197 ns clock:inst\|mhour11\[2\]~547 3 COMB LCCOMB_X22_Y10_N4 4 " "Info: 3: + IC(1.098 ns) + CELL(0.624 ns) = 10.197 ns; Loc. = LCCOMB_X22_Y10_N4; Fanout = 4; COMB Node = 'clock:inst\|mhour11\[2\]~547'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.722 ns" { K0~19 clock:inst|mhour11[2]~547 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.377 ns) + CELL(0.366 ns) 10.940 ns clock:inst\|mhour22\[3\]~566 4 COMB LCCOMB_X22_Y10_N0 4 " "Info: 4: + IC(0.377 ns) + CELL(0.366 ns) = 10.940 ns; Loc. = LCCOMB_X22_Y10_N0; Fanout = 4; COMB Node = 'clock:inst\|mhour22\[3\]~566'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.743 ns" { clock:inst|mhour11[2]~547 clock:inst|mhour22[3]~566 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.855 ns) 12.123 ns clock:inst\|mhour22\[0\] 5 REG LCFF_X22_Y10_N21 4 " "Info: 5: + IC(0.328 ns) + CELL(0.855 ns) = 12.123 ns; Loc. = LCFF_X22_Y10_N21; Fanout = 4; REG Node = 'clock:inst\|mhour22\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.183 ns" { clock:inst|mhour22[3]~566 clock:inst|mhour22[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.209 ns ( 26.47 % ) " "Info: Total cell delay = 3.209 ns ( 26.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.914 ns ( 73.53 % ) " "Info: Total interconnect delay = 8.914 ns ( 73.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { K0 K0~19 clock:inst|mhour11[2]~547 clock:inst|mhour22[3]~566 clock:inst|mhour22[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { K0 {} K0~combout {} K0~19 {} clock:inst|mhour11[2]~547 {} clock:inst|mhour22[3]~566 {} clock:inst|mhour22[0] {} } { 0.000ns 0.000ns 7.111ns 1.098ns 0.377ns 0.328ns } { 0.000ns 0.994ns 0.370ns 0.624ns 0.366ns 0.855ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.704 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to destination register is 6.704 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.970 ns) 3.682 ns FPQ:inst6\|QD 2 REG LCFF_X21_Y8_N17 6 " "Info: 2: + IC(1.572 ns) + CELL(0.970 ns) = 3.682 ns; Loc. = LCFF_X21_Y8_N17; Fanout = 6; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.000 ns) 5.183 ns FPQ:inst6\|QD~clkctrl 3 COMB CLKCTRL_G5 19 " "Info: 3: + IC(1.501 ns) + CELL(0.000 ns) = 5.183 ns; Loc. = CLKCTRL_G5; Fanout = 19; COMB Node = 'FPQ:inst6\|QD~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { FPQ:inst6|QD FPQ:inst6|QD~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.666 ns) 6.704 ns clock:inst\|mhour22\[0\] 4 REG LCFF_X22_Y10_N21 4 " "Info: 4: + IC(0.855 ns) + CELL(0.666 ns) = 6.704 ns; Loc. = LCFF_X22_Y10_N21; Fanout = 4; REG Node = 'clock:inst\|mhour22\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.521 ns" { FPQ:inst6|QD~clkctrl clock:inst|mhour22[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 41.41 % ) " "Info: Total cell delay = 2.776 ns ( 41.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.928 ns ( 58.59 % ) " "Info: Total interconnect delay = 3.928 ns ( 58.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.704 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mhour22[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.704 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mhour22[0] {} } { 0.000ns 0.000ns 1.572ns 1.501ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { K0 K0~19 clock:inst|mhour11[2]~547 clock:inst|mhour22[3]~566 clock:inst|mhour22[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { K0 {} K0~combout {} K0~19 {} clock:inst|mhour11[2]~547 {} clock:inst|mhour22[3]~566 {} clock:inst|mhour22[0] {} } { 0.000ns 0.000ns 7.111ns 1.098ns 0.377ns 0.328ns } { 0.000ns 0.994ns 0.370ns 0.624ns 0.366ns 0.855ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.704 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|mhour22[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.704 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|mhour22[0] {} } { 0.000ns 0.000ns 1.572ns 1.501ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "CLK led\[0\] seltime:inst2\|daout\[2\] 15.749 ns register " "Info: tco from clock \"CLK\" to destination pin \"led\[0\]\" through register \"seltime:inst2\|daout\[2\]\" is 15.749 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 9.415 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to source register is 9.415 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.970 ns) 3.682 ns FPQ:inst6\|QG 2 REG LCFF_X20_Y10_N15 3 " "Info: 2: + IC(1.572 ns) + CELL(0.970 ns) = 3.682 ns; Loc. = LCFF_X20_Y10_N15; Fanout = 3; REG Node = 'FPQ:inst6\|QG'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { CLK FPQ:inst6|QG } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.970 ns) 5.092 ns seltime:inst2\|count\[2\] 3 REG LCFF_X20_Y10_N5 18 " "Info: 3: + IC(0.440 ns) + CELL(0.970 ns) = 5.092 ns; Loc. = LCFF_X20_Y10_N5; Fanout = 18; REG Node = 'seltime:inst2\|count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.410 ns" { FPQ:inst6|QG seltime:inst2|count[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.546 ns) + CELL(0.366 ns) 6.004 ns seltime:inst2\|Mux1~19 4 COMB LCCOMB_X20_Y10_N18 1 " "Info: 4: + IC(0.546 ns) + CELL(0.366 ns) = 6.004 ns; Loc. = LCCOMB_X20_Y10_N18; Fanout = 1; COMB Node = 'seltime:inst2\|Mux1~19'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.912 ns" { seltime:inst2|count[2] seltime:inst2|Mux1~19 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.833 ns) + CELL(0.000 ns) 7.837 ns seltime:inst2\|Mux1~19clkctrl 5 COMB CLKCTRL_G4 5 " "Info: 5: + IC(1.833 ns) + CELL(0.000 ns) = 7.837 ns; Loc. = CLKCTRL_G4; Fanout = 5; COMB Node = 'seltime:inst2\|Mux1~19clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.833 ns" { seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.372 ns) + CELL(0.206 ns) 9.415 ns seltime:inst2\|daout\[2\] 6 REG LCCOMB_X24_Y9_N8 7 " "Info: 6: + IC(1.372 ns) + CELL(0.206 ns) = 9.415 ns; Loc. = LCCOMB_X24_Y9_N8; Fanout = 7; REG Node = 'seltime:inst2\|daout\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.578 ns" { seltime:inst2|Mux1~19clkctrl seltime:inst2|daout[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.652 ns ( 38.79 % ) " "Info: Total cell delay = 3.652 ns ( 38.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.763 ns ( 61.21 % ) " "Info: Total interconnect delay = 5.763 ns ( 61.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.415 ns" { CLK FPQ:inst6|QG seltime:inst2|count[2] seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl seltime:inst2|daout[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.415 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[2] {} seltime:inst2|Mux1~19 {} seltime:inst2|Mux1~19clkctrl {} seltime:inst2|daout[2] {} } { 0.000ns 0.000ns 1.572ns 0.440ns 0.546ns 1.833ns 1.372ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.366ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.334 ns + Longest register pin " "Info: + Longest register to pin delay is 6.334 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns seltime:inst2\|daout\[2\] 1 REG LCCOMB_X24_Y9_N8 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X24_Y9_N8; Fanout = 7; REG Node = 'seltime:inst2\|daout\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { seltime:inst2|daout[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.651 ns) 1.421 ns deled:inst4\|led\[0\]~725 2 COMB LCCOMB_X24_Y9_N24 1 " "Info: 2: + IC(0.770 ns) + CELL(0.651 ns) = 1.421 ns; Loc. = LCCOMB_X24_Y9_N24; Fanout = 1; COMB Node = 'deled:inst4\|led\[0\]~725'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.421 ns" { seltime:inst2|daout[2] deled:inst4|led[0]~725 } "NODE_NAME" } } { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.807 ns) + CELL(3.106 ns) 6.334 ns led\[0\] 3 PIN PIN_115 0 " "Info: 3: + IC(1.807 ns) + CELL(3.106 ns) = 6.334 ns; Loc. = PIN_115; Fanout = 0; PIN Node = 'led\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.913 ns" { deled:inst4|led[0]~725 led[0] } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 72 1040 1216 88 "led\[6..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.757 ns ( 59.31 % ) " "Info: Total cell delay = 3.757 ns ( 59.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.577 ns ( 40.69 % ) " "Info: Total interconnect delay = 2.577 ns ( 40.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.334 ns" { seltime:inst2|daout[2] deled:inst4|led[0]~725 led[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.334 ns" { seltime:inst2|daout[2] {} deled:inst4|led[0]~725 {} led[0] {} } { 0.000ns 0.770ns 1.807ns } { 0.000ns 0.651ns 3.106ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.415 ns" { CLK FPQ:inst6|QG seltime:inst2|count[2] seltime:inst2|Mux1~19 seltime:inst2|Mux1~19clkctrl seltime:inst2|daout[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.415 ns" { CLK {} CLK~combout {} FPQ:inst6|QG {} seltime:inst2|count[2] {} seltime:inst2|Mux1~19 {} seltime:inst2|Mux1~19clkctrl {} seltime:inst2|daout[2] {} } { 0.000ns 0.000ns 1.572ns 0.440ns 0.546ns 1.833ns 1.372ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.366ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.334 ns" { seltime:inst2|daout[2] deled:inst4|led[0]~725 led[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.334 ns" { seltime:inst2|daout[2] {} deled:inst4|led[0]~725 {} led[0] {} } { 0.000ns 0.770ns 1.807ns } { 0.000ns 0.651ns 3.106ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "clock:inst\|msecond1\[0\] K1 CLK -1.038 ns register " "Info: th for register \"clock:inst\|msecond1\[0\]\" (data pin = \"K1\", clock pin = \"CLK\") is -1.038 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 6.703 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 6.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.970 ns) 3.682 ns FPQ:inst6\|QD 2 REG LCFF_X21_Y8_N17 6 " "Info: 2: + IC(1.572 ns) + CELL(0.970 ns) = 3.682 ns; Loc. = LCFF_X21_Y8_N17; Fanout = 6; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.000 ns) 5.183 ns FPQ:inst6\|QD~clkctrl 3 COMB CLKCTRL_G5 19 " "Info: 3: + IC(1.501 ns) + CELL(0.000 ns) = 5.183 ns; Loc. = CLKCTRL_G5; Fanout = 19; COMB Node = 'FPQ:inst6\|QD~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { FPQ:inst6|QD FPQ:inst6|QD~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 6.703 ns clock:inst\|msecond1\[0\] 4 REG LCFF_X21_Y10_N15 6 " "Info: 4: + IC(0.854 ns) + CELL(0.666 ns) = 6.703 ns; Loc. = LCFF_X21_Y10_N15; Fanout = 6; REG Node = 'clock:inst\|msecond1\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.520 ns" { FPQ:inst6|QD~clkctrl clock:inst|msecond1[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 41.41 % ) " "Info: Total cell delay = 2.776 ns ( 41.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.927 ns ( 58.59 % ) " "Info: Total interconnect delay = 3.927 ns ( 58.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.703 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|msecond1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.703 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|msecond1[0] {} } { 0.000ns 0.000ns 1.572ns 1.501ns 0.854ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.047 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.047 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns K1 1 PIN PIN_99 18 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_99; Fanout = 18; PIN Node = 'K1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { K1 } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 160 -16 152 176 "K1" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.749 ns) + CELL(0.206 ns) 7.939 ns clock:inst\|msecond1~263 2 COMB LCCOMB_X21_Y10_N14 1 " "Info: 2: + IC(6.749 ns) + CELL(0.206 ns) = 7.939 ns; Loc. = LCCOMB_X21_Y10_N14; Fanout = 1; COMB Node = 'clock:inst\|msecond1~263'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.955 ns" { K1 clock:inst|msecond1~263 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 8.047 ns clock:inst\|msecond1\[0\] 3 REG LCFF_X21_Y10_N15 6 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 8.047 ns; Loc. = LCFF_X21_Y10_N15; Fanout = 6; REG Node = 'clock:inst\|msecond1\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { clock:inst|msecond1~263 clock:inst|msecond1[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.298 ns ( 16.13 % ) " "Info: Total cell delay = 1.298 ns ( 16.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.749 ns ( 83.87 % ) " "Info: Total interconnect delay = 6.749 ns ( 83.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.047 ns" { K1 clock:inst|msecond1~263 clock:inst|msecond1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.047 ns" { K1 {} K1~combout {} clock:inst|msecond1~263 {} clock:inst|msecond1[0] {} } { 0.000ns 0.000ns 6.749ns 0.000ns } { 0.000ns 0.984ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.703 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|msecond1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.703 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|msecond1[0] {} } { 0.000ns 0.000ns 1.572ns 1.501ns 0.854ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.047 ns" { K1 clock:inst|msecond1~263 clock:inst|msecond1[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.047 ns" { K1 {} K1~combout {} clock:inst|msecond1~263 {} clock:inst|msecond1[0] {} } { 0.000ns 0.000ns 6.749ns 0.000ns } { 0.000ns 0.984ns 0.206ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}