tm.tan.qmsg

基于fpga数字钟系统

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK register clock:inst\|msecond1\[1\] register clock:inst\|msecond1\[3\] 186.25 MHz 5.369 ns Internal " "Info: Clock \"CLK\" has Internal fmax of 186.25 MHz between source register \"clock:inst\|msecond1\[1\]\" and destination register \"clock:inst\|msecond1\[3\]\" (period= 5.369 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.153 ns + Longest register register " "Info: + Longest register to register delay is 3.153 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock:inst\|msecond1\[1\] 1 REG LCFF_X21_Y10_N5 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 5; REG Node = 'clock:inst\|msecond1\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock:inst|msecond1[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.747 ns) + CELL(0.624 ns) 1.371 ns clock:inst\|Equal0~57 2 COMB LCCOMB_X22_Y10_N28 5 " "Info: 2: + IC(0.747 ns) + CELL(0.624 ns) = 1.371 ns; Loc. = LCCOMB_X22_Y10_N28; Fanout = 5; COMB Node = 'clock:inst\|Equal0~57'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.371 ns" { clock:inst|msecond1[1] clock:inst|Equal0~57 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.050 ns) + CELL(0.624 ns) 3.045 ns clock:inst\|msecond1~262 3 COMB LCCOMB_X21_Y8_N30 1 " "Info: 3: + IC(1.050 ns) + CELL(0.624 ns) = 3.045 ns; Loc. = LCCOMB_X21_Y8_N30; Fanout = 1; COMB Node = 'clock:inst\|msecond1~262'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.674 ns" { clock:inst|Equal0~57 clock:inst|msecond1~262 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.153 ns clock:inst\|msecond1\[3\] 4 REG LCFF_X21_Y8_N31 4 " "Info: 4: + IC(0.000 ns) + CELL(0.108 ns) = 3.153 ns; Loc. = LCFF_X21_Y8_N31; Fanout = 4; REG Node = 'clock:inst\|msecond1\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { clock:inst|msecond1~262 clock:inst|msecond1[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.356 ns ( 43.01 % ) " "Info: Total cell delay = 1.356 ns ( 43.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.797 ns ( 56.99 % ) " "Info: Total interconnect delay = 1.797 ns ( 56.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.153 ns" { clock:inst|msecond1[1] clock:inst|Equal0~57 clock:inst|msecond1~262 clock:inst|msecond1[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.153 ns" { clock:inst|msecond1[1] {} clock:inst|Equal0~57 {} clock:inst|msecond1~262 {} clock:inst|msecond1[3] {} } { 0.000ns 0.747ns 1.050ns 0.000ns } { 0.000ns 0.624ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-1.952 ns - Smallest " "Info: - Smallest clock skew is -1.952 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 4.751 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK\" to destination register is 4.751 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.970 ns) 3.682 ns FPQ:inst6\|QD 2 REG LCFF_X21_Y8_N17 6 " "Info: 2: + IC(1.572 ns) + CELL(0.970 ns) = 3.682 ns; Loc. = LCFF_X21_Y8_N17; Fanout = 6; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.403 ns) + CELL(0.666 ns) 4.751 ns clock:inst\|msecond1\[3\] 3 REG LCFF_X21_Y8_N31 4 " "Info: 3: + IC(0.403 ns) + CELL(0.666 ns) = 4.751 ns; Loc. = LCFF_X21_Y8_N31; Fanout = 4; REG Node = 'clock:inst\|msecond1\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { FPQ:inst6|QD clock:inst|msecond1[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 58.43 % ) " "Info: Total cell delay = 2.776 ns ( 58.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.975 ns ( 41.57 % ) " "Info: Total interconnect delay = 1.975 ns ( 41.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { CLK FPQ:inst6|QD clock:inst|msecond1[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.751 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} clock:inst|msecond1[3] {} } { 0.000ns 0.000ns 1.572ns 0.403ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 6.703 ns - Longest register " "Info: - Longest clock path from clock \"CLK\" to source register is 6.703 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.970 ns) 3.682 ns FPQ:inst6\|QD 2 REG LCFF_X21_Y8_N17 6 " "Info: 2: + IC(1.572 ns) + CELL(0.970 ns) = 3.682 ns; Loc. = LCFF_X21_Y8_N17; Fanout = 6; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.501 ns) + CELL(0.000 ns) 5.183 ns FPQ:inst6\|QD~clkctrl 3 COMB CLKCTRL_G5 19 " "Info: 3: + IC(1.501 ns) + CELL(0.000 ns) = 5.183 ns; Loc. = CLKCTRL_G5; Fanout = 19; COMB Node = 'FPQ:inst6\|QD~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { FPQ:inst6|QD FPQ:inst6|QD~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 6.703 ns clock:inst\|msecond1\[1\] 4 REG LCFF_X21_Y10_N5 5 " "Info: 4: + IC(0.854 ns) + CELL(0.666 ns) = 6.703 ns; Loc. = LCFF_X21_Y10_N5; Fanout = 5; REG Node = 'clock:inst\|msecond1\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.520 ns" { FPQ:inst6|QD~clkctrl clock:inst|msecond1[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.776 ns ( 41.41 % ) " "Info: Total cell delay = 2.776 ns ( 41.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.927 ns ( 58.59 % ) " "Info: Total interconnect delay = 3.927 ns ( 58.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.703 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|msecond1[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.703 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|msecond1[1] {} } { 0.000ns 0.000ns 1.572ns 1.501ns 0.854ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { CLK FPQ:inst6|QD clock:inst|msecond1[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.751 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} clock:inst|msecond1[3] {} } { 0.000ns 0.000ns 1.572ns 0.403ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.703 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|msecond1[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.703 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|msecond1[1] {} } { 0.000ns 0.000ns 1.572ns 1.501ns 0.854ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.153 ns" { clock:inst|msecond1[1] clock:inst|Equal0~57 clock:inst|msecond1~262 clock:inst|msecond1[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.153 ns" { clock:inst|msecond1[1] {} clock:inst|Equal0~57 {} clock:inst|msecond1~262 {} clock:inst|msecond1[3] {} } { 0.000ns 0.747ns 1.050ns 0.000ns } { 0.000ns 0.624ns 0.624ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.751 ns" { CLK FPQ:inst6|QD clock:inst|msecond1[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.751 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} clock:inst|msecond1[3] {} } { 0.000ns 0.000ns 1.572ns 0.403ns } { 0.000ns 1.140ns 0.970ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.703 ns" { CLK FPQ:inst6|QD FPQ:inst6|QD~clkctrl clock:inst|msecond1[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.703 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} FPQ:inst6|QD~clkctrl {} clock:inst|msecond1[1] {} } { 0.000ns 0.000ns 1.572ns 1.501ns 0.854ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK 16 " "Warning: Circuit may not operate. Detected 16 non-operational path(s) clocked by clock \"CLK\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "FPQ:inst6\|M XS:inst1\|y CLK 4.968 ns " "Info: Found hold time violation between source  pin or register \"FPQ:inst6\|M\" and destination pin or register \"XS:inst1\|y\" for clock \"CLK\" (Hold time is 4.968 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.735 ns + Largest " "Info: + Largest clock skew is 6.735 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK destination 9.532 ns + Longest register " "Info: + Longest clock path from clock \"CLK\" to destination register is 9.532 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.572 ns) + CELL(0.970 ns) 3.682 ns FPQ:inst6\|QD 2 REG LCFF_X21_Y8_N17 6 " "Info: 2: + IC(1.572 ns) + CELL(0.970 ns) = 3.682 ns; Loc. = LCFF_X21_Y8_N17; Fanout = 6; REG Node = 'FPQ:inst6\|QD'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.542 ns" { CLK FPQ:inst6|QD } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.073 ns) + CELL(0.970 ns) 5.725 ns clock:inst\|msecond2\[0\] 3 REG LCFF_X22_Y8_N15 6 " "Info: 3: + IC(1.073 ns) + CELL(0.970 ns) = 5.725 ns; Loc. = LCFF_X22_Y8_N15; Fanout = 6; REG Node = 'clock:inst\|msecond2\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.043 ns" { FPQ:inst6|QD clock:inst|msecond2[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.616 ns) 6.826 ns XS:inst1\|process0~30 4 COMB LCCOMB_X22_Y8_N2 1 " "Info: 4: + IC(0.485 ns) + CELL(0.616 ns) = 6.826 ns; Loc. = LCCOMB_X22_Y8_N2; Fanout = 1; COMB Node = 'XS:inst1\|process0~30'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.101 ns" { clock:inst|msecond2[0] XS:inst1|process0~30 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.624 ns) 7.819 ns XS:inst1\|process0~0 5 COMB LCCOMB_X22_Y8_N16 1 " "Info: 5: + IC(0.369 ns) + CELL(0.624 ns) = 7.819 ns; Loc. = LCCOMB_X22_Y8_N16; Fanout = 1; COMB Node = 'XS:inst1\|process0~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.993 ns" { XS:inst1|process0~30 XS:inst1|process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.062 ns) + CELL(0.651 ns) 9.532 ns XS:inst1\|y 6 REG LCCOMB_X24_Y8_N0 1 " "Info: 6: + IC(1.062 ns) + CELL(0.651 ns) = 9.532 ns; Loc. = LCCOMB_X24_Y8_N0; Fanout = 1; REG Node = 'XS:inst1\|y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.713 ns" { XS:inst1|process0~0 XS:inst1|y } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.971 ns ( 52.15 % ) " "Info: Total cell delay = 4.971 ns ( 52.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 47.85 % ) " "Info: Total interconnect delay = 4.561 ns ( 47.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.532 ns" { CLK FPQ:inst6|QD clock:inst|msecond2[0] XS:inst1|process0~30 XS:inst1|process0~0 XS:inst1|y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.532 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} clock:inst|msecond2[0] {} XS:inst1|process0~30 {} XS:inst1|process0~0 {} XS:inst1|y {} } { 0.000ns 0.000ns 1.572ns 1.073ns 0.485ns 0.369ns 1.062ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.616ns 0.624ns 0.651ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK source 2.797 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK\" to source register is 2.797 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns CLK 1 CLK PIN_23 3 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 3; CLK Node = 'CLK'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLK } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns CLK~clkctrl 2 COMB CLKCTRL_G2 62 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 62; COMB Node = 'CLK~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { CLK CLK~clkctrl } "NODE_NAME" } } { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 56 -16 152 72 "CLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.848 ns) + CELL(0.666 ns) 2.797 ns FPQ:inst6\|M 3 REG LCFF_X26_Y9_N17 1 " "Info: 3: + IC(0.848 ns) + CELL(0.666 ns) = 2.797 ns; Loc. = LCFF_X26_Y9_N17; Fanout = 1; REG Node = 'FPQ:inst6\|M'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.514 ns" { CLK~clkctrl FPQ:inst6|M } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.57 % ) " "Info: Total cell delay = 1.806 ns ( 64.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.991 ns ( 35.43 % ) " "Info: Total interconnect delay = 0.991 ns ( 35.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.797 ns" { CLK CLK~clkctrl FPQ:inst6|M } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.797 ns" { CLK {} CLK~combout {} CLK~clkctrl {} FPQ:inst6|M {} } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.532 ns" { CLK FPQ:inst6|QD clock:inst|msecond2[0] XS:inst1|process0~30 XS:inst1|process0~0 XS:inst1|y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.532 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} clock:inst|msecond2[0] {} XS:inst1|process0~30 {} XS:inst1|process0~0 {} XS:inst1|y {} } { 0.000ns 0.000ns 1.572ns 1.073ns 0.485ns 0.369ns 1.062ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.616ns 0.624ns 0.651ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.797 ns" { CLK CLK~clkctrl FPQ:inst6|M } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.797 ns" { CLK {} CLK~combout {} CLK~clkctrl {} FPQ:inst6|M {} } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.463 ns - Shortest register register " "Info: - Shortest register to register delay is 1.463 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FPQ:inst6\|M 1 REG LCFF_X26_Y9_N17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y9_N17; Fanout = 1; REG Node = 'FPQ:inst6\|M'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { FPQ:inst6|M } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.097 ns) + CELL(0.366 ns) 1.463 ns XS:inst1\|y 2 REG LCCOMB_X24_Y8_N0 1 " "Info: 2: + IC(1.097 ns) + CELL(0.366 ns) = 1.463 ns; Loc. = LCCOMB_X24_Y8_N0; Fanout = 1; REG Node = 'XS:inst1\|y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.463 ns" { FPQ:inst6|M XS:inst1|y } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.366 ns ( 25.02 % ) " "Info: Total cell delay = 0.366 ns ( 25.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.097 ns ( 74.98 % ) " "Info: Total interconnect delay = 1.097 ns ( 74.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.463 ns" { FPQ:inst6|M XS:inst1|y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.463 ns" { FPQ:inst6|M {} XS:inst1|y {} } { 0.000ns 1.097ns } { 0.000ns 0.366ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 6 -1 0 } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "9.532 ns" { CLK FPQ:inst6|QD clock:inst|msecond2[0] XS:inst1|process0~30 XS:inst1|process0~0 XS:inst1|y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "9.532 ns" { CLK {} CLK~combout {} FPQ:inst6|QD {} clock:inst|msecond2[0] {} XS:inst1|process0~30 {} XS:inst1|process0~0 {} XS:inst1|y {} } { 0.000ns 0.000ns 1.572ns 1.073ns 0.485ns 0.369ns 1.062ns } { 0.000ns 1.140ns 0.970ns 0.970ns 0.616ns 0.624ns 0.651ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.797 ns" { CLK CLK~clkctrl FPQ:inst6|M } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.797 ns" { CLK {} CLK~combout {} CLK~clkctrl {} FPQ:inst6|M {} } { 0.000ns 0.000ns 0.143ns 0.848ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.463 ns" { FPQ:inst6|M XS:inst1|y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.463 ns" { FPQ:inst6|M {} XS:inst1|y {} } { 0.000ns 1.097ns } { 0.000ns 0.366ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}