tm.hier_info

基于fpga数字钟系统

|TM
h <= seltime:inst2.dp
CLK => FPQ:inst6.clk
K0 => clock:inst.set
K1 => clock:inst.s1
K2 => clock:inst.s2
K3 => clock:inst.s3
fenm <= XS:inst1.sc
led[0] <= deled:inst4.led[0]
led[1] <= deled:inst4.led[1]
led[2] <= deled:inst4.led[2]
led[3] <= deled:inst4.led[3]
led[4] <= deled:inst4.led[4]
led[5] <= deled:inst4.led[5]
led[6] <= deled:inst4.led[6]
yma[0] <= YIMA:inst3.y[0]
yma[1] <= YIMA:inst3.y[1]
yma[2] <= YIMA:inst3.y[2]
yma[3] <= YIMA:inst3.y[3]
yma[4] <= YIMA:inst3.y[4]
yma[5] <= YIMA:inst3.y[5]
yma[6] <= YIMA:inst3.y[6]
yma[7] <= YIMA:inst3.y[7]


|TM|seltime:inst2
sec0[0] => Mux2.IN2
sec0[1] => Mux3.IN2
sec0[2] => Mux4.IN2
sec0[3] => Mux5.IN2
sec1[0] => Mux2.IN3
sec1[1] => Mux3.IN3
sec1[2] => Mux4.IN3
sec1[3] => Mux5.IN3
min0[0] => Mux2.IN4
min0[1] => Mux3.IN4
min0[2] => Mux4.IN4
min0[3] => Mux5.IN4
min1[0] => Mux2.IN5
min1[1] => Mux3.IN5
min1[2] => Mux4.IN5
min1[3] => Mux5.IN5
hh0[0] => Mux2.IN6
hh0[1] => Mux3.IN6
hh0[2] => Mux4.IN6
hh0[3] => Mux5.IN6
hh1[0] => Mux2.IN7
hh1[1] => Mux3.IN7
hh1[2] => Mux4.IN7
hh1[3] => Mux5.IN7
clk1 => count[2].CLK
clk1 => count[1].CLK
clk1 => count[0].CLK
daout[0] <= daout[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
daout[1] <= daout[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
daout[2] <= daout[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
daout[3] <= daout[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
dp <= dp$latch.DB_MAX_OUTPUT_PORT_TYPE
sel[0] <= count[0].DB_MAX_OUTPUT_PORT_TYPE
sel[1] <= count[1].DB_MAX_OUTPUT_PORT_TYPE
sel[2] <= count[2].DB_MAX_OUTPUT_PORT_TYPE


|TM|FPQ:inst6
clk => count[25].CLK
clk => count[24].CLK
clk => count[23].CLK
clk => count[22].CLK
clk => count[21].CLK
clk => count[20].CLK
clk => count[19].CLK
clk => count[18].CLK
clk => count[17].CLK
clk => count[16].CLK
clk => count[15].CLK
clk => count[14].CLK
clk => count[13].CLK
clk => count[12].CLK
clk => count[11].CLK
clk => count[10].CLK
clk => count[9].CLK
clk => count[8].CLK
clk => count[7].CLK
clk => count[6].CLK
clk => count[5].CLK
clk => count[4].CLK
clk => count[3].CLK
clk => count[2].CLK
clk => count[1].CLK
clk => count[0].CLK
clk => QD~reg0.CLK
clk => MOUNT[11].CLK
clk => MOUNT[10].CLK
clk => MOUNT[9].CLK
clk => MOUNT[8].CLK
clk => MOUNT[7].CLK
clk => MOUNT[6].CLK
clk => MOUNT[5].CLK
clk => MOUNT[4].CLK
clk => MOUNT[3].CLK
clk => MOUNT[2].CLK
clk => MOUNT[1].CLK
clk => MOUNT[0].CLK
clk => QG~reg0.CLK
clk => fmq[22].CLK
clk => fmq[21].CLK
clk => fmq[20].CLK
clk => fmq[19].CLK
clk => fmq[18].CLK
clk => fmq[17].CLK
clk => fmq[16].CLK
clk => fmq[15].CLK
clk => fmq[14].CLK
clk => fmq[13].CLK
clk => fmq[12].CLK
clk => fmq[11].CLK
clk => fmq[10].CLK
clk => fmq[9].CLK
clk => fmq[8].CLK
clk => fmq[7].CLK
clk => fmq[6].CLK
clk => fmq[5].CLK
clk => fmq[4].CLK
clk => fmq[3].CLK
clk => fmq[2].CLK
clk => fmq[1].CLK
clk => fmq[0].CLK
clk => M~reg0.CLK
QG <= QG~reg0.DB_MAX_OUTPUT_PORT_TYPE
QD <= QD~reg0.DB_MAX_OUTPUT_PORT_TYPE
M <= M~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TM|clock:inst
clk => mminite1[3].CLK
clk => mminite1[2].CLK
clk => mminite1[1].CLK
clk => mminite1[0].CLK
clk => mminite2[3].CLK
clk => mminite2[2].CLK
clk => mminite2[1].CLK
clk => mminite2[0].CLK
clk => mhour11[3].CLK
clk => mhour11[2].CLK
clk => mhour11[1].CLK
clk => mhour11[0].CLK
clk => mhour22[3].CLK
clk => mhour22[2].CLK
clk => mhour22[1].CLK
clk => mhour22[0].CLK
clk => msecond1[3].CLK
clk => msecond1[2].CLK
clk => msecond1[1].CLK
clk => msecond1[0].CLK
clk => msecond2[3].CLK
clk => msecond2[2].CLK
clk => msecond2[1].CLK
clk => msecond2[0].CLK
clk => cout~reg0.CLK
set => mhour22~39.OUTPUTSELECT
set => mhour22~38.OUTPUTSELECT
set => mhour22~37.OUTPUTSELECT
set => mhour22~36.OUTPUTSELECT
set => mhour11~35.OUTPUTSELECT
set => mhour11~34.OUTPUTSELECT
set => mhour11~33.OUTPUTSELECT
set => mhour11~32.OUTPUTSELECT
set => mminite2~27.OUTPUTSELECT
set => mminite2~26.OUTPUTSELECT
set => mminite2~25.OUTPUTSELECT
set => mminite2~24.OUTPUTSELECT
set => mminite1~23.OUTPUTSELECT
set => mminite1~22.OUTPUTSELECT
set => mminite1~21.OUTPUTSELECT
set => mminite1~20.OUTPUTSELECT
set => msecond2[1].ENA
set => msecond2[0].ENA
set => cout~reg0.ENA
set => msecond2[2].ENA
set => msecond2[3].ENA
set => msecond1[0].ENA
set => msecond1[1].ENA
set => msecond1[2].ENA
set => msecond1[3].ENA
s1 => cout~2.OUTPUTSELECT
s1 => msecond2~11.OUTPUTSELECT
s1 => msecond2~10.OUTPUTSELECT
s1 => msecond2~9.OUTPUTSELECT
s1 => msecond2~8.OUTPUTSELECT
s1 => msecond1~7.OUTPUTSELECT
s1 => msecond1~6.OUTPUTSELECT
s1 => msecond1~5.OUTPUTSELECT
s1 => msecond1~4.OUTPUTSELECT
s1 => mhour22~35.OUTPUTSELECT
s1 => mhour22~34.OUTPUTSELECT
s1 => mhour22~33.OUTPUTSELECT
s1 => mhour22~32.OUTPUTSELECT
s1 => mhour11~31.OUTPUTSELECT
s1 => mhour11~30.OUTPUTSELECT
s1 => mhour11~29.OUTPUTSELECT
s1 => mhour11~28.OUTPUTSELECT
s1 => mminite2~23.OUTPUTSELECT
s1 => mminite2~22.OUTPUTSELECT
s1 => mminite2~21.OUTPUTSELECT
s1 => mminite2~20.OUTPUTSELECT
s1 => mminite1~19.OUTPUTSELECT
s1 => mminite1~18.OUTPUTSELECT
s1 => mminite1~17.OUTPUTSELECT
s1 => mminite1~16.OUTPUTSELECT
s2 => mminite2~3.OUTPUTSELECT
s2 => mminite2~2.OUTPUTSELECT
s2 => mminite2~1.OUTPUTSELECT
s2 => mminite2~0.OUTPUTSELECT
s2 => mminite1~3.OUTPUTSELECT
s2 => mminite1~2.OUTPUTSELECT
s2 => mminite1~1.OUTPUTSELECT
s2 => mminite1~0.OUTPUTSELECT
s3 => mhour22~3.OUTPUTSELECT
s3 => mhour22~2.OUTPUTSELECT
s3 => mhour22~1.OUTPUTSELECT
s3 => mhour22~0.OUTPUTSELECT
s3 => mhour11~3.OUTPUTSELECT
s3 => mhour11~2.OUTPUTSELECT
s3 => mhour11~1.OUTPUTSELECT
s3 => mhour11~0.OUTPUTSELECT
second1[0] <= msecond1[0].DB_MAX_OUTPUT_PORT_TYPE
second1[1] <= msecond1[1].DB_MAX_OUTPUT_PORT_TYPE
second1[2] <= msecond1[2].DB_MAX_OUTPUT_PORT_TYPE
second1[3] <= msecond1[3].DB_MAX_OUTPUT_PORT_TYPE
second2[0] <= msecond2[0].DB_MAX_OUTPUT_PORT_TYPE
second2[1] <= msecond2[1].DB_MAX_OUTPUT_PORT_TYPE
second2[2] <= msecond2[2].DB_MAX_OUTPUT_PORT_TYPE
second2[3] <= msecond2[3].DB_MAX_OUTPUT_PORT_TYPE
minite1[0] <= mminite1[0].DB_MAX_OUTPUT_PORT_TYPE
minite1[1] <= mminite1[1].DB_MAX_OUTPUT_PORT_TYPE
minite1[2] <= mminite1[2].DB_MAX_OUTPUT_PORT_TYPE
minite1[3] <= mminite1[3].DB_MAX_OUTPUT_PORT_TYPE
minite2[0] <= mminite2[0].DB_MAX_OUTPUT_PORT_TYPE
minite2[1] <= mminite2[1].DB_MAX_OUTPUT_PORT_TYPE
minite2[2] <= mminite2[2].DB_MAX_OUTPUT_PORT_TYPE
minite2[3] <= mminite2[3].DB_MAX_OUTPUT_PORT_TYPE
hour1[0] <= mhour11[0].DB_MAX_OUTPUT_PORT_TYPE
hour1[1] <= mhour11[1].DB_MAX_OUTPUT_PORT_TYPE
hour1[2] <= mhour11[2].DB_MAX_OUTPUT_PORT_TYPE
hour1[3] <= mhour11[3].DB_MAX_OUTPUT_PORT_TYPE
hour2[0] <= mhour22[0].DB_MAX_OUTPUT_PORT_TYPE
hour2[1] <= mhour22[1].DB_MAX_OUTPUT_PORT_TYPE
hour2[2] <= mhour22[2].DB_MAX_OUTPUT_PORT_TYPE
hour2[3] <= mhour22[3].DB_MAX_OUTPUT_PORT_TYPE
cout <= cout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|TM|XS:inst1
clk => y.DATAIN
a1[0] => Equal0.IN7
a1[1] => Equal0.IN6
a1[2] => Equal0.IN5
a1[3] => Equal0.IN4
a0[0] => LessThan0.IN8
a0[1] => LessThan0.IN7
a0[2] => LessThan0.IN6
a0[3] => LessThan0.IN5
sc <= y.DB_MAX_OUTPUT_PORT_TYPE


|TM|deled:inst4
num[0] => Equal15.IN7
num[0] => Equal14.IN7
num[0] => Equal13.IN7
num[0] => Equal12.IN7
num[0] => Equal11.IN7
num[0] => Equal10.IN7
num[0] => Equal9.IN7
num[0] => Equal8.IN7
num[0] => Equal7.IN7
num[0] => Equal6.IN7
num[0] => Equal5.IN7
num[0] => Equal4.IN7
num[0] => Equal3.IN7
num[0] => Equal2.IN7
num[0] => Equal1.IN7
num[0] => Equal0.IN7
num[1] => Equal15.IN6
num[1] => Equal14.IN6
num[1] => Equal13.IN6
num[1] => Equal12.IN6
num[1] => Equal11.IN6
num[1] => Equal10.IN6
num[1] => Equal9.IN6
num[1] => Equal8.IN6
num[1] => Equal7.IN6
num[1] => Equal6.IN6
num[1] => Equal5.IN6
num[1] => Equal4.IN6
num[1] => Equal3.IN6
num[1] => Equal2.IN6
num[1] => Equal1.IN6
num[1] => Equal0.IN6
num[2] => Equal15.IN5
num[2] => Equal14.IN5
num[2] => Equal13.IN5
num[2] => Equal12.IN5
num[2] => Equal11.IN5
num[2] => Equal10.IN5
num[2] => Equal9.IN5
num[2] => Equal8.IN5
num[2] => Equal7.IN5
num[2] => Equal6.IN5
num[2] => Equal5.IN5
num[2] => Equal4.IN5
num[2] => Equal3.IN5
num[2] => Equal2.IN5
num[2] => Equal1.IN5
num[2] => Equal0.IN5
num[3] => Equal15.IN4
num[3] => Equal14.IN4
num[3] => Equal13.IN4
num[3] => Equal12.IN4
num[3] => Equal11.IN4
num[3] => Equal10.IN4
num[3] => Equal9.IN4
num[3] => Equal8.IN4
num[3] => Equal7.IN4
num[3] => Equal6.IN4
num[3] => Equal5.IN4
num[3] => Equal4.IN4
num[3] => Equal3.IN4
num[3] => Equal2.IN4
num[3] => Equal1.IN4
num[3] => Equal0.IN4
led[0] <= led[0]$latch.DB_MAX_OUTPUT_PORT_TYPE
led[1] <= led[1]$latch.DB_MAX_OUTPUT_PORT_TYPE
led[2] <= led[2]$latch.DB_MAX_OUTPUT_PORT_TYPE
led[3] <= led[3]$latch.DB_MAX_OUTPUT_PORT_TYPE
led[4] <= led[4]$latch.DB_MAX_OUTPUT_PORT_TYPE
led[5] <= led[5]$latch.DB_MAX_OUTPUT_PORT_TYPE
led[6] <= led[6]$latch.DB_MAX_OUTPUT_PORT_TYPE


|TM|YIMA:inst3
a[0] => Mux7.IN10
a[0] => Mux6.IN10
a[0] => Mux5.IN10
a[0] => Mux4.IN10
a[0] => Mux3.IN10
a[0] => Mux2.IN10
a[0] => Mux1.IN10
a[0] => Mux0.IN10
a[1] => Mux7.IN9
a[1] => Mux6.IN9
a[1] => Mux5.IN9
a[1] => Mux4.IN9
a[1] => Mux3.IN9
a[1] => Mux2.IN9
a[1] => Mux1.IN9
a[1] => Mux0.IN9
a[2] => Mux7.IN8
a[2] => Mux6.IN8
a[2] => Mux5.IN8
a[2] => Mux4.IN8
a[2] => Mux3.IN8
a[2] => Mux2.IN8
a[2] => Mux1.IN8
a[2] => Mux0.IN8
y[0] <= Mux7.DB_MAX_OUTPUT_PORT_TYPE
y[1] <= Mux6.DB_MAX_OUTPUT_PORT_TYPE
y[2] <= Mux5.DB_MAX_OUTPUT_PORT_TYPE
y[3] <= Mux4.DB_MAX_OUTPUT_PORT_TYPE
y[4] <= Mux3.DB_MAX_OUTPUT_PORT_TYPE
y[5] <= Mux2.DB_MAX_OUTPUT_PORT_TYPE
y[6] <= Mux1.DB_MAX_OUTPUT_PORT_TYPE
y[7] <= Mux0.DB_MAX_OUTPUT_PORT_TYPE