prev_cmp_seltime.map.qmsg

基于fpga数字钟系统

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 27 18:14:14 2008 " "Info: Processing started: Thu Nov 27 18:14:14 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off seltime -c seltime " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off seltime -c seltime" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "seltime.vhd 2 1 " "Warning: Using design file seltime.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seltime-fun " "Info: Found design unit 1: seltime-fun" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 seltime " "Info: Found entity 1: seltime" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "seltime " "Info: Elaborating entity \"seltime\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count seltime.vhd(28) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(28): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec0 seltime.vhd(29) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(29): signal \"sec0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec1 seltime.vhd(30) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(30): signal \"sec1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min0 seltime.vhd(31) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(31): signal \"min0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min1 seltime.vhd(32) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(32): signal \"min1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hh0 seltime.vhd(33) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(33): signal \"hh0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 33 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hh1 seltime.vhd(34) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(34): signal \"hh1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 34 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "daout seltime.vhd(17) " "Warning (10631): VHDL Process Statement warning at seltime.vhd(17): inferring latch(es) for signal or variable \"daout\", which holds its previous value in one or more paths through the process" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dp seltime.vhd(17) " "Warning (10631): VHDL Process Statement warning at seltime.vhd(17): inferring latch(es) for signal or variable \"dp\", which holds its previous value in one or more paths through the process" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dp seltime.vhd(17) " "Info (10041): Inferred latch for \"dp\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[0\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[0\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[1\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[1\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[2\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[2\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[3\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[3\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "daout\[0\]\$latch " "Warning: Latch daout\[0\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[2\]" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "daout\[1\]\$latch " "Warning: Latch daout\[1\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[2\]" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "daout\[2\]\$latch " "Warning: Latch daout\[2\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[2\]" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "daout\[3\]\$latch " "Warning: Latch daout\[3\]\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[2\]" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "dp\$latch " "Warning: Latch dp\$latch has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[1\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[1\]" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "62 " "Info: Implemented 62 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "26 " "Info: Implemented 26 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "8 " "Info: Implemented 8 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "28 " "Info: Implemented 28 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 20 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 27 18:14:16 2008 " "Info: Processing ended: Thu Nov 27 18:14:16 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}