seltime.tan.qmsg

基于fpga数字钟系统

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "count\[1\] daout\[3\]\$latch clk1 3.718 ns " "Info: Found hold time violation between source  pin or register \"count\[1\]\" and destination pin or register \"daout\[3\]\$latch\" for clock \"clk1\" (Hold time is 3.718 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.813 ns + Largest " "Info: + Largest clock skew is 5.813 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 8.812 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 8.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_188 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.970 ns) 3.303 ns count\[2\] 2 REG LCFF_X12_Y10_N5 11 " "Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.303 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { clk1 count[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.624 ns) 4.738 ns Mux6~18 3 COMB LCCOMB_X13_Y10_N0 1 " "Info: 3: + IC(0.811 ns) + CELL(0.624 ns) = 4.738 ns; Loc. = LCCOMB_X13_Y10_N0; Fanout = 1; COMB Node = 'Mux6~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.435 ns" { count[2] Mux6~18 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.535 ns) + CELL(0.000 ns) 7.273 ns Mux6~18clkctrl 4 COMB CLKCTRL_G3 5 " "Info: 4: + IC(2.535 ns) + CELL(0.000 ns) = 7.273 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'Mux6~18clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { Mux6~18 Mux6~18clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.333 ns) + CELL(0.206 ns) 8.812 ns daout\[3\]\$latch 5 REG LCCOMB_X13_Y10_N28 1 " "Info: 5: + IC(1.333 ns) + CELL(0.206 ns) = 8.812 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; REG Node = 'daout\[3\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.784 ns ( 31.59 % ) " "Info: Total cell delay = 2.784 ns ( 31.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.028 ns ( 68.41 % ) " "Info: Total interconnect delay = 6.028 ns ( 68.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.812 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.812 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.349ns 0.811ns 2.535ns 1.333ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 2.999 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to source register is 2.999 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_188 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.666 ns) 2.999 ns count\[1\] 2 REG LCFF_X12_Y10_N31 12 " "Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.999 ns; Loc. = LCFF_X12_Y10_N31; Fanout = 12; REG Node = 'count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.015 ns" { clk1 count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 55.02 % ) " "Info: Total cell delay = 1.650 ns ( 55.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.349 ns ( 44.98 % ) " "Info: Total interconnect delay = 1.349 ns ( 44.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk1 count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk1 {} clk1~combout {} count[1] {} } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.812 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.812 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.349ns 0.811ns 2.535ns 1.333ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk1 count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk1 {} clk1~combout {} count[1] {} } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.791 ns - Shortest register register " "Info: - Shortest register to register delay is 1.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LCFF_X12_Y10_N31 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y10_N31; Fanout = 12; REG Node = 'count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.690 ns) + CELL(0.366 ns) 1.056 ns Mux5~195 2 COMB LCCOMB_X13_Y10_N8 1 " "Info: 2: + IC(0.690 ns) + CELL(0.366 ns) = 1.056 ns; Loc. = LCCOMB_X13_Y10_N8; Fanout = 1; COMB Node = 'Mux5~195'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.056 ns" { count[1] Mux5~195 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.370 ns) 1.791 ns daout\[3\]\$latch 3 REG LCCOMB_X13_Y10_N28 1 " "Info: 3: + IC(0.365 ns) + CELL(0.370 ns) = 1.791 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; REG Node = 'daout\[3\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { Mux5~195 daout[3]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.736 ns ( 41.09 % ) " "Info: Total cell delay = 0.736 ns ( 41.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.055 ns ( 58.91 % ) " "Info: Total interconnect delay = 1.055 ns ( 58.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { count[1] Mux5~195 daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.791 ns" { count[1] {} Mux5~195 {} daout[3]$latch {} } { 0.000ns 0.690ns 0.365ns } { 0.000ns 0.366ns 0.370ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.812 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.812 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.349ns 0.811ns 2.535ns 1.333ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.999 ns" { clk1 count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.999 ns" { clk1 {} clk1~combout {} count[1] {} } { 0.000ns 0.000ns 1.349ns } { 0.000ns 0.984ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.791 ns" { count[1] Mux5~195 daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "1.791 ns" { count[1] {} Mux5~195 {} daout[3]$latch {} } { 0.000ns 0.690ns 0.365ns } { 0.000ns 0.366ns 0.370ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "daout\[2\]\$latch min0\[2\] clk1 3.848 ns register " "Info: tsu for register \"daout\[2\]\$latch\" (data pin = \"min0\[2\]\", clock pin = \"clk1\") is 3.848 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.070 ns + Longest pin register " "Info: + Longest pin to register delay is 11.070 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.004 ns) 1.004 ns min0\[2\] 1 PIN PIN_206 1 " "Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 1; PIN Node = 'min0\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { min0[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.839 ns) + CELL(0.651 ns) 8.494 ns Mux4~193 2 COMB LCCOMB_X12_Y10_N22 1 " "Info: 2: + IC(6.839 ns) + CELL(0.651 ns) = 8.494 ns; Loc. = LCCOMB_X12_Y10_N22; Fanout = 1; COMB Node = 'Mux4~193'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.490 ns" { min0[2] Mux4~193 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.206 ns) 9.061 ns Mux4~194 3 COMB LCCOMB_X12_Y10_N10 1 " "Info: 3: + IC(0.361 ns) + CELL(0.206 ns) = 9.061 ns; Loc. = LCCOMB_X12_Y10_N10; Fanout = 1; COMB Node = 'Mux4~194'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.567 ns" { Mux4~193 Mux4~194 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.387 ns) + CELL(0.206 ns) 9.654 ns Mux4~196 4 COMB LCCOMB_X12_Y10_N2 1 " "Info: 4: + IC(0.387 ns) + CELL(0.206 ns) = 9.654 ns; Loc. = LCCOMB_X12_Y10_N2; Fanout = 1; COMB Node = 'Mux4~196'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.593 ns" { Mux4~194 Mux4~196 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.046 ns) + CELL(0.370 ns) 11.070 ns daout\[2\]\$latch 5 REG LCCOMB_X10_Y10_N0 1 " "Info: 5: + IC(1.046 ns) + CELL(0.370 ns) = 11.070 ns; Loc. = LCCOMB_X10_Y10_N0; Fanout = 1; REG Node = 'daout\[2\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.416 ns" { Mux4~196 daout[2]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.437 ns ( 22.01 % ) " "Info: Total cell delay = 2.437 ns ( 22.01 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.633 ns ( 77.99 % ) " "Info: Total interconnect delay = 8.633 ns ( 77.99 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.070 ns" { min0[2] Mux4~193 Mux4~194 Mux4~196 daout[2]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.070 ns" { min0[2] {} min0[2]~combout {} Mux4~193 {} Mux4~194 {} Mux4~196 {} daout[2]$latch {} } { 0.000ns 0.000ns 6.839ns 0.361ns 0.387ns 1.046ns } { 0.000ns 1.004ns 0.651ns 0.206ns 0.206ns 0.370ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.197 ns + " "Info: + Micro setup delay of destination is 1.197 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 8.419 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 8.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_188 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.970 ns) 3.303 ns count\[1\] 2 REG LCFF_X12_Y10_N31 12 " "Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.303 ns; Loc. = LCFF_X12_Y10_N31; Fanout = 12; REG Node = 'count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { clk1 count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.691 ns) + CELL(0.370 ns) 4.364 ns Mux6~18 3 COMB LCCOMB_X13_Y10_N0 1 " "Info: 3: + IC(0.691 ns) + CELL(0.370 ns) = 4.364 ns; Loc. = LCCOMB_X13_Y10_N0; Fanout = 1; COMB Node = 'Mux6~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.061 ns" { count[1] Mux6~18 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.535 ns) + CELL(0.000 ns) 6.899 ns Mux6~18clkctrl 4 COMB CLKCTRL_G3 5 " "Info: 4: + IC(2.535 ns) + CELL(0.000 ns) = 6.899 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'Mux6~18clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { Mux6~18 Mux6~18clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.314 ns) + CELL(0.206 ns) 8.419 ns daout\[2\]\$latch 5 REG LCCOMB_X10_Y10_N0 1 " "Info: 5: + IC(1.314 ns) + CELL(0.206 ns) = 8.419 ns; Loc. = LCCOMB_X10_Y10_N0; Fanout = 1; REG Node = 'daout\[2\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.520 ns" { Mux6~18clkctrl daout[2]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.530 ns ( 30.05 % ) " "Info: Total cell delay = 2.530 ns ( 30.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.889 ns ( 69.95 % ) " "Info: Total interconnect delay = 5.889 ns ( 69.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[2]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[2]$latch {} } { 0.000ns 0.000ns 1.349ns 0.691ns 2.535ns 1.314ns } { 0.000ns 0.984ns 0.970ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "11.070 ns" { min0[2] Mux4~193 Mux4~194 Mux4~196 daout[2]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "11.070 ns" { min0[2] {} min0[2]~combout {} Mux4~193 {} Mux4~194 {} Mux4~196 {} daout[2]$latch {} } { 0.000ns 0.000ns 6.839ns 0.361ns 0.387ns 1.046ns } { 0.000ns 1.004ns 0.651ns 0.206ns 0.206ns 0.370ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.419 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[2]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.419 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[2]$latch {} } { 0.000ns 0.000ns 1.349ns 0.691ns 2.535ns 1.314ns } { 0.000ns 0.984ns 0.970ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 dp dp\$latch 14.304 ns register " "Info: tco from clock \"clk1\" to destination pin \"dp\" through register \"dp\$latch\" is 14.304 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 8.812 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 8.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_188 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.970 ns) 3.303 ns count\[2\] 2 REG LCFF_X12_Y10_N5 11 " "Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.303 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { clk1 count[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.624 ns) 4.738 ns Mux6~18 3 COMB LCCOMB_X13_Y10_N0 1 " "Info: 3: + IC(0.811 ns) + CELL(0.624 ns) = 4.738 ns; Loc. = LCCOMB_X13_Y10_N0; Fanout = 1; COMB Node = 'Mux6~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.435 ns" { count[2] Mux6~18 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.535 ns) + CELL(0.000 ns) 7.273 ns Mux6~18clkctrl 4 COMB CLKCTRL_G3 5 " "Info: 4: + IC(2.535 ns) + CELL(0.000 ns) = 7.273 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'Mux6~18clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { Mux6~18 Mux6~18clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.333 ns) + CELL(0.206 ns) 8.812 ns dp\$latch 5 REG LCCOMB_X13_Y10_N24 1 " "Info: 5: + IC(1.333 ns) + CELL(0.206 ns) = 8.812 ns; Loc. = LCCOMB_X13_Y10_N24; Fanout = 1; REG Node = 'dp\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { Mux6~18clkctrl dp$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.784 ns ( 31.59 % ) " "Info: Total cell delay = 2.784 ns ( 31.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.028 ns ( 68.41 % ) " "Info: Total interconnect delay = 6.028 ns ( 68.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.812 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl dp$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.812 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} dp$latch {} } { 0.000ns 0.000ns 1.349ns 0.811ns 2.535ns 1.333ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.492 ns + Longest register pin " "Info: + Longest register to pin delay is 5.492 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dp\$latch 1 REG LCCOMB_X13_Y10_N24 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X13_Y10_N24; Fanout = 1; REG Node = 'dp\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { dp$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.206 ns) + CELL(3.286 ns) 5.492 ns dp 2 PIN PIN_68 0 " "Info: 2: + IC(2.206 ns) + CELL(3.286 ns) = 5.492 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'dp'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.492 ns" { dp$latch dp } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.286 ns ( 59.83 % ) " "Info: Total cell delay = 3.286 ns ( 59.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.206 ns ( 40.17 % ) " "Info: Total interconnect delay = 2.206 ns ( 40.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.492 ns" { dp$latch dp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.492 ns" { dp$latch {} dp {} } { 0.000ns 2.206ns } { 0.000ns 3.286ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.812 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl dp$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.812 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} dp$latch {} } { 0.000ns 0.000ns 1.349ns 0.811ns 2.535ns 1.333ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.492 ns" { dp$latch dp } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.492 ns" { dp$latch {} dp {} } { 0.000ns 2.206ns } { 0.000ns 3.286ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "daout\[3\]\$latch min1\[3\] clk1 -0.066 ns register " "Info: th for register \"daout\[3\]\$latch\" (data pin = \"min1\[3\]\", clock pin = \"clk1\") is -0.066 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 8.812 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 8.812 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_188 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.349 ns) + CELL(0.970 ns) 3.303 ns count\[2\] 2 REG LCFF_X12_Y10_N5 11 " "Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.303 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.319 ns" { clk1 count[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.811 ns) + CELL(0.624 ns) 4.738 ns Mux6~18 3 COMB LCCOMB_X13_Y10_N0 1 " "Info: 3: + IC(0.811 ns) + CELL(0.624 ns) = 4.738 ns; Loc. = LCCOMB_X13_Y10_N0; Fanout = 1; COMB Node = 'Mux6~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.435 ns" { count[2] Mux6~18 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.535 ns) + CELL(0.000 ns) 7.273 ns Mux6~18clkctrl 4 COMB CLKCTRL_G3 5 " "Info: 4: + IC(2.535 ns) + CELL(0.000 ns) = 7.273 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'Mux6~18clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.535 ns" { Mux6~18 Mux6~18clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.333 ns) + CELL(0.206 ns) 8.812 ns daout\[3\]\$latch 5 REG LCCOMB_X13_Y10_N28 1 " "Info: 5: + IC(1.333 ns) + CELL(0.206 ns) = 8.812 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; REG Node = 'daout\[3\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.784 ns ( 31.59 % ) " "Info: Total cell delay = 2.784 ns ( 31.59 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.028 ns ( 68.41 % ) " "Info: Total interconnect delay = 6.028 ns ( 68.41 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.812 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.812 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.349ns 0.811ns 2.535ns 1.333ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.878 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.878 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns min1\[3\] 1 PIN PIN_181 1 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_181; Fanout = 1; PIN Node = 'min1\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { min1[3] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.964 ns) + CELL(0.624 ns) 7.572 ns Mux5~193 2 COMB LCCOMB_X13_Y10_N2 1 " "Info: 2: + IC(5.964 ns) + CELL(0.624 ns) = 7.572 ns; Loc. = LCCOMB_X13_Y10_N2; Fanout = 1; COMB Node = 'Mux5~193'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.588 ns" { min1[3] Mux5~193 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 8.143 ns Mux5~195 3 COMB LCCOMB_X13_Y10_N8 1 " "Info: 3: + IC(0.365 ns) + CELL(0.206 ns) = 8.143 ns; Loc. = LCCOMB_X13_Y10_N8; Fanout = 1; COMB Node = 'Mux5~195'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { Mux5~193 Mux5~195 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.370 ns) 8.878 ns daout\[3\]\$latch 4 REG LCCOMB_X13_Y10_N28 1 " "Info: 4: + IC(0.365 ns) + CELL(0.370 ns) = 8.878 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; REG Node = 'daout\[3\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { Mux5~195 daout[3]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.184 ns ( 24.60 % ) " "Info: Total cell delay = 2.184 ns ( 24.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.694 ns ( 75.40 % ) " "Info: Total interconnect delay = 6.694 ns ( 75.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.878 ns" { min1[3] Mux5~193 Mux5~195 daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.878 ns" { min1[3] {} min1[3]~combout {} Mux5~193 {} Mux5~195 {} daout[3]$latch {} } { 0.000ns 0.000ns 5.964ns 0.365ns 0.365ns } { 0.000ns 0.984ns 0.624ns 0.206ns 0.370ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.812 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.812 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.349ns 0.811ns 2.535ns 1.333ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.878 ns" { min1[3] Mux5~193 Mux5~195 daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.878 ns" { min1[3] {} min1[3]~combout {} Mux5~193 {} Mux5~195 {} daout[3]$latch {} } { 0.000ns 0.000ns 5.964ns 0.365ns 0.365ns } { 0.000ns 0.984ns 0.624ns 0.206ns 0.370ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}