prev_cmp_seltime.tan.qmsg

基于fpga数字钟系统

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "count\[1\] daout\[3\]\$latch clk1 3.25 ns " "Info: Found hold time violation between source  pin or register \"count\[1\]\" and destination pin or register \"daout\[3\]\$latch\" for clock \"clk1\" (Hold time is 3.25 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.638 ns + Largest " "Info: + Largest clock skew is 5.638 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 8.858 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 8.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_180 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_180; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(0.970 ns) 3.524 ns count\[1\] 2 REG LCFF_X13_Y11_N13 12 " "Info: 2: + IC(1.570 ns) + CELL(0.970 ns) = 3.524 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 12; REG Node = 'count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.540 ns" { clk1 count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.624 ns) 4.981 ns Mux6~18 3 COMB LCCOMB_X12_Y11_N28 1 " "Info: 3: + IC(0.833 ns) + CELL(0.624 ns) = 4.981 ns; Loc. = LCCOMB_X12_Y11_N28; Fanout = 1; COMB Node = 'Mux6~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.457 ns" { count[1] Mux6~18 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.137 ns) + CELL(0.000 ns) 7.118 ns Mux6~18clkctrl 4 COMB CLKCTRL_G5 5 " "Info: 4: + IC(2.137 ns) + CELL(0.000 ns) = 7.118 ns; Loc. = CLKCTRL_G5; Fanout = 5; COMB Node = 'Mux6~18clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.137 ns" { Mux6~18 Mux6~18clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.370 ns) + CELL(0.370 ns) 8.858 ns daout\[3\]\$latch 5 REG LCCOMB_X12_Y11_N0 1 " "Info: 5: + IC(1.370 ns) + CELL(0.370 ns) = 8.858 ns; Loc. = LCCOMB_X12_Y11_N0; Fanout = 1; REG Node = 'daout\[3\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.740 ns" { Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.948 ns ( 33.28 % ) " "Info: Total cell delay = 2.948 ns ( 33.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.910 ns ( 66.72 % ) " "Info: Total interconnect delay = 5.910 ns ( 66.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.858 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.858 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.570ns 0.833ns 2.137ns 1.370ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.370ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 3.220 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to source register is 3.220 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_180 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_180; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(0.666 ns) 3.220 ns count\[1\] 2 REG LCFF_X13_Y11_N13 12 " "Info: 2: + IC(1.570 ns) + CELL(0.666 ns) = 3.220 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 12; REG Node = 'count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.236 ns" { clk1 count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.650 ns ( 51.24 % ) " "Info: Total cell delay = 1.650 ns ( 51.24 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.570 ns ( 48.76 % ) " "Info: Total interconnect delay = 1.570 ns ( 48.76 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.220 ns" { clk1 count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.220 ns" { clk1 {} clk1~combout {} count[1] {} } { 0.000ns 0.000ns 1.570ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.858 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.858 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.570ns 0.833ns 2.137ns 1.370ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.370ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.220 ns" { clk1 count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.220 ns" { clk1 {} clk1~combout {} count[1] {} } { 0.000ns 0.000ns 1.570ns } { 0.000ns 0.984ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.084 ns - Shortest register register " "Info: - Shortest register to register delay is 2.084 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[1\] 1 REG LCFF_X13_Y11_N13 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 12; REG Node = 'count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.838 ns) + CELL(0.366 ns) 1.204 ns Mux5~195 2 COMB LCCOMB_X12_Y11_N20 1 " "Info: 2: + IC(0.838 ns) + CELL(0.366 ns) = 1.204 ns; Loc. = LCCOMB_X12_Y11_N20; Fanout = 1; COMB Node = 'Mux5~195'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.204 ns" { count[1] Mux5~195 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.674 ns) + CELL(0.206 ns) 2.084 ns daout\[3\]\$latch 3 REG LCCOMB_X12_Y11_N0 1 " "Info: 3: + IC(0.674 ns) + CELL(0.206 ns) = 2.084 ns; Loc. = LCCOMB_X12_Y11_N0; Fanout = 1; REG Node = 'daout\[3\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.880 ns" { Mux5~195 daout[3]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.572 ns ( 27.45 % ) " "Info: Total cell delay = 0.572 ns ( 27.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.512 ns ( 72.55 % ) " "Info: Total interconnect delay = 1.512 ns ( 72.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.084 ns" { count[1] Mux5~195 daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.084 ns" { count[1] {} Mux5~195 {} daout[3]$latch {} } { 0.000ns 0.838ns 0.674ns } { 0.000ns 0.366ns 0.206ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.858 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.858 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.570ns 0.833ns 2.137ns 1.370ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.370ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.220 ns" { clk1 count[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.220 ns" { clk1 {} clk1~combout {} count[1] {} } { 0.000ns 0.000ns 1.570ns } { 0.000ns 0.984ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.084 ns" { count[1] Mux5~195 daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.084 ns" { count[1] {} Mux5~195 {} daout[3]$latch {} } { 0.000ns 0.838ns 0.674ns } { 0.000ns 0.366ns 0.206ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "daout\[1\]\$latch hh1\[1\] clk1 3.731 ns register " "Info: tsu for register \"daout\[1\]\$latch\" (data pin = \"hh1\[1\]\", clock pin = \"clk1\") is 3.731 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.514 ns + Longest pin register " "Info: + Longest pin to register delay is 10.514 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns hh1\[1\] 1 PIN PIN_169 1 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_169; Fanout = 1; PIN Node = 'hh1\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { hh1[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.654 ns) + CELL(0.624 ns) 8.262 ns Mux3~193 2 COMB LCCOMB_X13_Y11_N18 1 " "Info: 2: + IC(6.654 ns) + CELL(0.624 ns) = 8.262 ns; Loc. = LCCOMB_X13_Y11_N18; Fanout = 1; COMB Node = 'Mux3~193'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.278 ns" { hh1[1] Mux3~193 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.716 ns) + CELL(0.206 ns) 9.184 ns Mux3~194 3 COMB LCCOMB_X13_Y11_N0 1 " "Info: 3: + IC(0.716 ns) + CELL(0.206 ns) = 9.184 ns; Loc. = LCCOMB_X13_Y11_N0; Fanout = 1; COMB Node = 'Mux3~194'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.922 ns" { Mux3~193 Mux3~194 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.206 ns) 9.759 ns Mux3~196 4 COMB LCCOMB_X13_Y11_N20 1 " "Info: 4: + IC(0.369 ns) + CELL(0.206 ns) = 9.759 ns; Loc. = LCCOMB_X13_Y11_N20; Fanout = 1; COMB Node = 'Mux3~196'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.575 ns" { Mux3~194 Mux3~196 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.385 ns) + CELL(0.370 ns) 10.514 ns daout\[1\]\$latch 5 REG LCCOMB_X13_Y11_N28 1 " "Info: 5: + IC(0.385 ns) + CELL(0.370 ns) = 10.514 ns; Loc. = LCCOMB_X13_Y11_N28; Fanout = 1; REG Node = 'daout\[1\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.755 ns" { Mux3~196 daout[1]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.390 ns ( 22.73 % ) " "Info: Total cell delay = 2.390 ns ( 22.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.124 ns ( 77.27 % ) " "Info: Total interconnect delay = 8.124 ns ( 77.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.514 ns" { hh1[1] Mux3~193 Mux3~194 Mux3~196 daout[1]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.514 ns" { hh1[1] {} hh1[1]~combout {} Mux3~193 {} Mux3~194 {} Mux3~196 {} daout[1]$latch {} } { 0.000ns 0.000ns 6.654ns 0.716ns 0.369ns 0.385ns } { 0.000ns 0.984ns 0.624ns 0.206ns 0.206ns 0.370ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.599 ns + " "Info: + Micro setup delay of destination is 1.599 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 8.382 ns - Shortest register " "Info: - Shortest clock path from clock \"clk1\" to destination register is 8.382 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_180 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_180; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(0.970 ns) 3.524 ns count\[2\] 2 REG LCFF_X13_Y11_N15 11 " "Info: 2: + IC(1.570 ns) + CELL(0.970 ns) = 3.524 ns; Loc. = LCFF_X13_Y11_N15; Fanout = 11; REG Node = 'count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.540 ns" { clk1 count[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.780 ns) + CELL(0.370 ns) 4.674 ns Mux6~18 3 COMB LCCOMB_X12_Y11_N28 1 " "Info: 3: + IC(0.780 ns) + CELL(0.370 ns) = 4.674 ns; Loc. = LCCOMB_X12_Y11_N28; Fanout = 1; COMB Node = 'Mux6~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.150 ns" { count[2] Mux6~18 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.137 ns) + CELL(0.000 ns) 6.811 ns Mux6~18clkctrl 4 COMB CLKCTRL_G5 5 " "Info: 4: + IC(2.137 ns) + CELL(0.000 ns) = 6.811 ns; Loc. = CLKCTRL_G5; Fanout = 5; COMB Node = 'Mux6~18clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.137 ns" { Mux6~18 Mux6~18clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.206 ns) 8.382 ns daout\[1\]\$latch 5 REG LCCOMB_X13_Y11_N28 1 " "Info: 5: + IC(1.365 ns) + CELL(0.206 ns) = 8.382 ns; Loc. = LCCOMB_X13_Y11_N28; Fanout = 1; REG Node = 'daout\[1\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { Mux6~18clkctrl daout[1]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.530 ns ( 30.18 % ) " "Info: Total cell delay = 2.530 ns ( 30.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.852 ns ( 69.82 % ) " "Info: Total interconnect delay = 5.852 ns ( 69.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.382 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl daout[1]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.382 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} daout[1]$latch {} } { 0.000ns 0.000ns 1.570ns 0.780ns 2.137ns 1.365ns } { 0.000ns 0.984ns 0.970ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.514 ns" { hh1[1] Mux3~193 Mux3~194 Mux3~196 daout[1]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.514 ns" { hh1[1] {} hh1[1]~combout {} Mux3~193 {} Mux3~194 {} Mux3~196 {} daout[1]$latch {} } { 0.000ns 0.000ns 6.654ns 0.716ns 0.369ns 0.385ns } { 0.000ns 0.984ns 0.624ns 0.206ns 0.206ns 0.370ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.382 ns" { clk1 count[2] Mux6~18 Mux6~18clkctrl daout[1]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.382 ns" { clk1 {} clk1~combout {} count[2] {} Mux6~18 {} Mux6~18clkctrl {} daout[1]$latch {} } { 0.000ns 0.000ns 1.570ns 0.780ns 2.137ns 1.365ns } { 0.000ns 0.984ns 0.970ns 0.370ns 0.000ns 0.206ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk1 daout\[3\] daout\[3\]\$latch 13.899 ns register " "Info: tco from clock \"clk1\" to destination pin \"daout\[3\]\" through register \"daout\[3\]\$latch\" is 13.899 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 source 8.858 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to source register is 8.858 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_180 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_180; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(0.970 ns) 3.524 ns count\[1\] 2 REG LCFF_X13_Y11_N13 12 " "Info: 2: + IC(1.570 ns) + CELL(0.970 ns) = 3.524 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 12; REG Node = 'count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.540 ns" { clk1 count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.624 ns) 4.981 ns Mux6~18 3 COMB LCCOMB_X12_Y11_N28 1 " "Info: 3: + IC(0.833 ns) + CELL(0.624 ns) = 4.981 ns; Loc. = LCCOMB_X12_Y11_N28; Fanout = 1; COMB Node = 'Mux6~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.457 ns" { count[1] Mux6~18 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.137 ns) + CELL(0.000 ns) 7.118 ns Mux6~18clkctrl 4 COMB CLKCTRL_G5 5 " "Info: 4: + IC(2.137 ns) + CELL(0.000 ns) = 7.118 ns; Loc. = CLKCTRL_G5; Fanout = 5; COMB Node = 'Mux6~18clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.137 ns" { Mux6~18 Mux6~18clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.370 ns) + CELL(0.370 ns) 8.858 ns daout\[3\]\$latch 5 REG LCCOMB_X12_Y11_N0 1 " "Info: 5: + IC(1.370 ns) + CELL(0.370 ns) = 8.858 ns; Loc. = LCCOMB_X12_Y11_N0; Fanout = 1; REG Node = 'daout\[3\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.740 ns" { Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.948 ns ( 33.28 % ) " "Info: Total cell delay = 2.948 ns ( 33.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.910 ns ( 66.72 % ) " "Info: Total interconnect delay = 5.910 ns ( 66.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.858 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.858 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.570ns 0.833ns 2.137ns 1.370ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.370ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.041 ns + Longest register pin " "Info: + Longest register to pin delay is 5.041 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns daout\[3\]\$latch 1 REG LCCOMB_X12_Y11_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X12_Y11_N0; Fanout = 1; REG Node = 'daout\[3\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { daout[3]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.775 ns) + CELL(3.266 ns) 5.041 ns daout\[3\] 2 PIN PIN_75 0 " "Info: 2: + IC(1.775 ns) + CELL(3.266 ns) = 5.041 ns; Loc. = PIN_75; Fanout = 0; PIN Node = 'daout\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.041 ns" { daout[3]$latch daout[3] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.266 ns ( 64.79 % ) " "Info: Total cell delay = 3.266 ns ( 64.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.775 ns ( 35.21 % ) " "Info: Total interconnect delay = 1.775 ns ( 35.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.041 ns" { daout[3]$latch daout[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.041 ns" { daout[3]$latch {} daout[3] {} } { 0.000ns 1.775ns } { 0.000ns 3.266ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.858 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[3]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.858 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[3]$latch {} } { 0.000ns 0.000ns 1.570ns 0.833ns 2.137ns 1.370ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.370ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.041 ns" { daout[3]$latch daout[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.041 ns" { daout[3]$latch {} daout[3] {} } { 0.000ns 1.775ns } { 0.000ns 3.266ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "daout\[1\]\$latch min1\[1\] clk1 -0.205 ns register " "Info: th for register \"daout\[1\]\$latch\" (data pin = \"min1\[1\]\", clock pin = \"clk1\") is -0.205 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk1 destination 8.689 ns + Longest register " "Info: + Longest clock path from clock \"clk1\" to destination register is 8.689 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns clk1 1 CLK PIN_180 3 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_180; Fanout = 3; CLK Node = 'clk1'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk1 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.570 ns) + CELL(0.970 ns) 3.524 ns count\[1\] 2 REG LCFF_X13_Y11_N13 12 " "Info: 2: + IC(1.570 ns) + CELL(0.970 ns) = 3.524 ns; Loc. = LCFF_X13_Y11_N13; Fanout = 12; REG Node = 'count\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.540 ns" { clk1 count[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.833 ns) + CELL(0.624 ns) 4.981 ns Mux6~18 3 COMB LCCOMB_X12_Y11_N28 1 " "Info: 3: + IC(0.833 ns) + CELL(0.624 ns) = 4.981 ns; Loc. = LCCOMB_X12_Y11_N28; Fanout = 1; COMB Node = 'Mux6~18'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.457 ns" { count[1] Mux6~18 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.137 ns) + CELL(0.000 ns) 7.118 ns Mux6~18clkctrl 4 COMB CLKCTRL_G5 5 " "Info: 4: + IC(2.137 ns) + CELL(0.000 ns) = 7.118 ns; Loc. = CLKCTRL_G5; Fanout = 5; COMB Node = 'Mux6~18clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.137 ns" { Mux6~18 Mux6~18clkctrl } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.365 ns) + CELL(0.206 ns) 8.689 ns daout\[1\]\$latch 5 REG LCCOMB_X13_Y11_N28 1 " "Info: 5: + IC(1.365 ns) + CELL(0.206 ns) = 8.689 ns; Loc. = LCCOMB_X13_Y11_N28; Fanout = 1; REG Node = 'daout\[1\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.571 ns" { Mux6~18clkctrl daout[1]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.784 ns ( 32.04 % ) " "Info: Total cell delay = 2.784 ns ( 32.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.905 ns ( 67.96 % ) " "Info: Total interconnect delay = 5.905 ns ( 67.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.689 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[1]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.689 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[1]$latch {} } { 0.000ns 0.000ns 1.570ns 0.833ns 2.137ns 1.365ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.894 ns - Shortest pin register " "Info: - Shortest pin to register delay is 8.894 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns min1\[1\] 1 PIN PIN_181 1 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_181; Fanout = 1; PIN Node = 'min1\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { min1[1] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.956 ns) + CELL(0.624 ns) 7.564 ns Mux3~194 2 COMB LCCOMB_X13_Y11_N0 1 " "Info: 2: + IC(5.956 ns) + CELL(0.624 ns) = 7.564 ns; Loc. = LCCOMB_X13_Y11_N0; Fanout = 1; COMB Node = 'Mux3~194'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.580 ns" { min1[1] Mux3~194 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.369 ns) + CELL(0.206 ns) 8.139 ns Mux3~196 3 COMB LCCOMB_X13_Y11_N20 1 " "Info: 3: + IC(0.369 ns) + CELL(0.206 ns) = 8.139 ns; Loc. = LCCOMB_X13_Y11_N20; Fanout = 1; COMB Node = 'Mux3~196'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.575 ns" { Mux3~194 Mux3~196 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.385 ns) + CELL(0.370 ns) 8.894 ns daout\[1\]\$latch 4 REG LCCOMB_X13_Y11_N28 1 " "Info: 4: + IC(0.385 ns) + CELL(0.370 ns) = 8.894 ns; Loc. = LCCOMB_X13_Y11_N28; Fanout = 1; REG Node = 'daout\[1\]\$latch'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.755 ns" { Mux3~196 daout[1]$latch } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.184 ns ( 24.56 % ) " "Info: Total cell delay = 2.184 ns ( 24.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.710 ns ( 75.44 % ) " "Info: Total interconnect delay = 6.710 ns ( 75.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.894 ns" { min1[1] Mux3~194 Mux3~196 daout[1]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.894 ns" { min1[1] {} min1[1]~combout {} Mux3~194 {} Mux3~196 {} daout[1]$latch {} } { 0.000ns 0.000ns 5.956ns 0.369ns 0.385ns } { 0.000ns 0.984ns 0.624ns 0.206ns 0.370ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.689 ns" { clk1 count[1] Mux6~18 Mux6~18clkctrl daout[1]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.689 ns" { clk1 {} clk1~combout {} count[1] {} Mux6~18 {} Mux6~18clkctrl {} daout[1]$latch {} } { 0.000ns 0.000ns 1.570ns 0.833ns 2.137ns 1.365ns } { 0.000ns 0.984ns 0.970ns 0.624ns 0.000ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "8.894 ns" { min1[1] Mux3~194 Mux3~196 daout[1]$latch } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "8.894 ns" { min1[1] {} min1[1]~combout {} Mux3~194 {} Mux3~196 {} daout[1]$latch {} } { 0.000ns 0.000ns 5.956ns 0.369ns 0.385ns } { 0.000ns 0.984ns 0.624ns 0.206ns 0.370ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}