prev_cmp_tm.qmsg

基于fpga数字钟系统

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Nov 28 21:15:19 2008 " "Info: Processing started: Fri Nov 28 21:15:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off TM -c TM " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TM -c TM" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "TM.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file TM.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 TM " "Info: Found entity 1: TM" {  } { { "TM.bdf" "" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "deled.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file deled.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 deled-fun " "Info: Found design unit 1: deled-fun" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 deled " "Info: Found entity 1: deled" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "XS.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file XS.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 XS-m " "Info: Found design unit 1: XS-m" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 XS " "Info: Found entity 1: XS" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "TM " "Info: Elaborating entity \"TM\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "seltime.vhd 2 1 " "Warning: Using design file seltime.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seltime-fun " "Info: Found design unit 1: seltime-fun" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 seltime " "Info: Found entity 1: seltime" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "seltime seltime:inst2 " "Info: Elaborating entity \"seltime\" for hierarchy \"seltime:inst2\"" {  } { { "TM.bdf" "inst2" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 48 632 792 208 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count seltime.vhd(26) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(26): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 26 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec0 seltime.vhd(27) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(27): signal \"sec0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 27 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "sec1 seltime.vhd(28) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(28): signal \"sec1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 28 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min0 seltime.vhd(29) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(29): signal \"min0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 29 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "min1 seltime.vhd(30) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(30): signal \"min1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 30 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hh0 seltime.vhd(31) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(31): signal \"hh0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 31 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "hh1 seltime.vhd(32) " "Warning (10492): VHDL Process Statement warning at seltime.vhd(32): signal \"hh1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 32 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "daout seltime.vhd(17) " "Warning (10631): VHDL Process Statement warning at seltime.vhd(17): inferring latch(es) for signal or variable \"daout\", which holds its previous value in one or more paths through the process" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "dp seltime.vhd(17) " "Warning (10631): VHDL Process Statement warning at seltime.vhd(17): inferring latch(es) for signal or variable \"dp\", which holds its previous value in one or more paths through the process" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "dp seltime.vhd(17) " "Info (10041): Inferred latch for \"dp\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[0\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[0\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[1\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[1\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[2\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[2\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[3\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[3\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}