prev_cmp_fpq.tan.qmsg

基于fpga数字钟系统

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 5 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register count\[0\] register count\[25\] 197.32 MHz 5.068 ns Internal " "Info: Clock \"clk\" has Internal fmax of 197.32 MHz between source register \"count\[0\]\" and destination register \"count\[25\]\" (period= 5.068 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.808 ns + Longest register register " "Info: + Longest register to register delay is 4.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LCFF_X8_Y4_N7 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X8_Y4_N7; Fanout = 3; REG Node = 'count\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[0] } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.472 ns) + CELL(0.621 ns) 1.093 ns Add0~313 2 COMB LCCOMB_X8_Y4_N6 2 " "Info: 2: + IC(0.472 ns) + CELL(0.621 ns) = 1.093 ns; Loc. = LCCOMB_X8_Y4_N6; Fanout = 2; COMB Node = 'Add0~313'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.093 ns" { count[0] Add0~313 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.179 ns Add0~315 3 COMB LCCOMB_X8_Y4_N8 2 " "Info: 3: + IC(0.000 ns) + CELL(0.086 ns) = 1.179 ns; Loc. = LCCOMB_X8_Y4_N8; Fanout = 2; COMB Node = 'Add0~315'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~313 Add0~315 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.265 ns Add0~317 4 COMB LCCOMB_X8_Y4_N10 2 " "Info: 4: + IC(0.000 ns) + CELL(0.086 ns) = 1.265 ns; Loc. = LCCOMB_X8_Y4_N10; Fanout = 2; COMB Node = 'Add0~317'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~315 Add0~317 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.351 ns Add0~319 5 COMB LCCOMB_X8_Y4_N12 2 " "Info: 5: + IC(0.000 ns) + CELL(0.086 ns) = 1.351 ns; Loc. = LCCOMB_X8_Y4_N12; Fanout = 2; COMB Node = 'Add0~319'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~317 Add0~319 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 1.541 ns Add0~321 6 COMB LCCOMB_X8_Y4_N14 2 " "Info: 6: + IC(0.000 ns) + CELL(0.190 ns) = 1.541 ns; Loc. = LCCOMB_X8_Y4_N14; Fanout = 2; COMB Node = 'Add0~321'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~319 Add0~321 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.627 ns Add0~323 7 COMB LCCOMB_X8_Y4_N16 2 " "Info: 7: + IC(0.000 ns) + CELL(0.086 ns) = 1.627 ns; Loc. = LCCOMB_X8_Y4_N16; Fanout = 2; COMB Node = 'Add0~323'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~321 Add0~323 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.713 ns Add0~325 8 COMB LCCOMB_X8_Y4_N18 2 " "Info: 8: + IC(0.000 ns) + CELL(0.086 ns) = 1.713 ns; Loc. = LCCOMB_X8_Y4_N18; Fanout = 2; COMB Node = 'Add0~325'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~323 Add0~325 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.799 ns Add0~327 9 COMB LCCOMB_X8_Y4_N20 2 " "Info: 9: + IC(0.000 ns) + CELL(0.086 ns) = 1.799 ns; Loc. = LCCOMB_X8_Y4_N20; Fanout = 2; COMB Node = 'Add0~327'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~325 Add0~327 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.885 ns Add0~329 10 COMB LCCOMB_X8_Y4_N22 2 " "Info: 10: + IC(0.000 ns) + CELL(0.086 ns) = 1.885 ns; Loc. = LCCOMB_X8_Y4_N22; Fanout = 2; COMB Node = 'Add0~329'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~327 Add0~329 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 1.971 ns Add0~331 11 COMB LCCOMB_X8_Y4_N24 2 " "Info: 11: + IC(0.000 ns) + CELL(0.086 ns) = 1.971 ns; Loc. = LCCOMB_X8_Y4_N24; Fanout = 2; COMB Node = 'Add0~331'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~329 Add0~331 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.057 ns Add0~333 12 COMB LCCOMB_X8_Y4_N26 2 " "Info: 12: + IC(0.000 ns) + CELL(0.086 ns) = 2.057 ns; Loc. = LCCOMB_X8_Y4_N26; Fanout = 2; COMB Node = 'Add0~333'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~331 Add0~333 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.143 ns Add0~335 13 COMB LCCOMB_X8_Y4_N28 2 " "Info: 13: + IC(0.000 ns) + CELL(0.086 ns) = 2.143 ns; Loc. = LCCOMB_X8_Y4_N28; Fanout = 2; COMB Node = 'Add0~335'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~333 Add0~335 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.175 ns) 2.318 ns Add0~337 14 COMB LCCOMB_X8_Y4_N30 2 " "Info: 14: + IC(0.000 ns) + CELL(0.175 ns) = 2.318 ns; Loc. = LCCOMB_X8_Y4_N30; Fanout = 2; COMB Node = 'Add0~337'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.175 ns" { Add0~335 Add0~337 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.404 ns Add0~339 15 COMB LCCOMB_X8_Y3_N0 2 " "Info: 15: + IC(0.000 ns) + CELL(0.086 ns) = 2.404 ns; Loc. = LCCOMB_X8_Y3_N0; Fanout = 2; COMB Node = 'Add0~339'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~337 Add0~339 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.490 ns Add0~341 16 COMB LCCOMB_X8_Y3_N2 2 " "Info: 16: + IC(0.000 ns) + CELL(0.086 ns) = 2.490 ns; Loc. = LCCOMB_X8_Y3_N2; Fanout = 2; COMB Node = 'Add0~341'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~339 Add0~341 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.576 ns Add0~343 17 COMB LCCOMB_X8_Y3_N4 2 " "Info: 17: + IC(0.000 ns) + CELL(0.086 ns) = 2.576 ns; Loc. = LCCOMB_X8_Y3_N4; Fanout = 2; COMB Node = 'Add0~343'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~341 Add0~343 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.662 ns Add0~345 18 COMB LCCOMB_X8_Y3_N6 2 " "Info: 18: + IC(0.000 ns) + CELL(0.086 ns) = 2.662 ns; Loc. = LCCOMB_X8_Y3_N6; Fanout = 2; COMB Node = 'Add0~345'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~343 Add0~345 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.748 ns Add0~347 19 COMB LCCOMB_X8_Y3_N8 2 " "Info: 19: + IC(0.000 ns) + CELL(0.086 ns) = 2.748 ns; Loc. = LCCOMB_X8_Y3_N8; Fanout = 2; COMB Node = 'Add0~347'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~345 Add0~347 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.834 ns Add0~349 20 COMB LCCOMB_X8_Y3_N10 2 " "Info: 20: + IC(0.000 ns) + CELL(0.086 ns) = 2.834 ns; Loc. = LCCOMB_X8_Y3_N10; Fanout = 2; COMB Node = 'Add0~349'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~347 Add0~349 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 2.920 ns Add0~351 21 COMB LCCOMB_X8_Y3_N12 2 " "Info: 21: + IC(0.000 ns) + CELL(0.086 ns) = 2.920 ns; Loc. = LCCOMB_X8_Y3_N12; Fanout = 2; COMB Node = 'Add0~351'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~349 Add0~351 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.190 ns) 3.110 ns Add0~353 22 COMB LCCOMB_X8_Y3_N14 2 " "Info: 22: + IC(0.000 ns) + CELL(0.190 ns) = 3.110 ns; Loc. = LCCOMB_X8_Y3_N14; Fanout = 2; COMB Node = 'Add0~353'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.190 ns" { Add0~351 Add0~353 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.196 ns Add0~355 23 COMB LCCOMB_X8_Y3_N16 2 " "Info: 23: + IC(0.000 ns) + CELL(0.086 ns) = 3.196 ns; Loc. = LCCOMB_X8_Y3_N16; Fanout = 2; COMB Node = 'Add0~355'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~353 Add0~355 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.282 ns Add0~357 24 COMB LCCOMB_X8_Y3_N18 2 " "Info: 24: + IC(0.000 ns) + CELL(0.086 ns) = 3.282 ns; Loc. = LCCOMB_X8_Y3_N18; Fanout = 2; COMB Node = 'Add0~357'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~355 Add0~357 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.368 ns Add0~359 25 COMB LCCOMB_X8_Y3_N20 2 " "Info: 25: + IC(0.000 ns) + CELL(0.086 ns) = 3.368 ns; Loc. = LCCOMB_X8_Y3_N20; Fanout = 2; COMB Node = 'Add0~359'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~357 Add0~359 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.086 ns) 3.454 ns Add0~361 26 COMB LCCOMB_X8_Y3_N22 1 " "Info: 26: + IC(0.000 ns) + CELL(0.086 ns) = 3.454 ns; Loc. = LCCOMB_X8_Y3_N22; Fanout = 1; COMB Node = 'Add0~361'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.086 ns" { Add0~359 Add0~361 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.506 ns) 3.960 ns Add0~362 27 COMB LCCOMB_X8_Y3_N24 1 " "Info: 27: + IC(0.000 ns) + CELL(0.506 ns) = 3.960 ns; Loc. = LCCOMB_X8_Y3_N24; Fanout = 1; COMB Node = 'Add0~362'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.506 ns" { Add0~361 Add0~362 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.370 ns) + CELL(0.370 ns) 4.700 ns count~282 28 COMB LCCOMB_X8_Y3_N28 1 " "Info: 28: + IC(0.370 ns) + CELL(0.370 ns) = 4.700 ns; Loc. = LCCOMB_X8_Y3_N28; Fanout = 1; COMB Node = 'count~282'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.740 ns" { Add0~362 count~282 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.808 ns count\[25\] 29 REG LCFF_X8_Y3_N29 3 " "Info: 29: + IC(0.000 ns) + CELL(0.108 ns) = 4.808 ns; Loc. = LCFF_X8_Y3_N29; Fanout = 3; REG Node = 'count\[25\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { count~282 count[25] } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.966 ns ( 82.49 % ) " "Info: Total cell delay = 3.966 ns ( 82.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.842 ns ( 17.51 % ) " "Info: Total interconnect delay = 0.842 ns ( 17.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.808 ns" { count[0] Add0~313 Add0~315 Add0~317 Add0~319 Add0~321 Add0~323 Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~343 Add0~345 Add0~347 Add0~349 Add0~351 Add0~353 Add0~355 Add0~357 Add0~359 Add0~361 Add0~362 count~282 count[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.808 ns" { count[0] {} Add0~313 {} Add0~315 {} Add0~317 {} Add0~319 {} Add0~321 {} Add0~323 {} Add0~325 {} Add0~327 {} Add0~329 {} Add0~331 {} Add0~333 {} Add0~335 {} Add0~337 {} Add0~339 {} Add0~341 {} Add0~343 {} Add0~345 {} Add0~347 {} Add0~349 {} Add0~351 {} Add0~353 {} Add0~355 {} Add0~357 {} Add0~359 {} Add0~361 {} Add0~362 {} count~282 {} count[25] {} } { 0.000ns 0.472ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.370ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.004 ns - Smallest " "Info: - Smallest clock skew is 0.004 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.788 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.839 ns) + CELL(0.666 ns) 2.788 ns count\[25\] 3 REG LCFF_X8_Y3_N29 3 " "Info: 3: + IC(0.839 ns) + CELL(0.666 ns) = 2.788 ns; Loc. = LCFF_X8_Y3_N29; Fanout = 3; REG Node = 'count\[25\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.505 ns" { clk~clkctrl count[25] } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.78 % ) " "Info: Total cell delay = 1.806 ns ( 64.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.982 ns ( 35.22 % ) " "Info: Total interconnect delay = 0.982 ns ( 35.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl count[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} count[25] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.784 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.784 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.835 ns) + CELL(0.666 ns) 2.784 ns count\[0\] 3 REG LCFF_X8_Y4_N7 3 " "Info: 3: + IC(0.835 ns) + CELL(0.666 ns) = 2.784 ns; Loc. = LCFF_X8_Y4_N7; Fanout = 3; REG Node = 'count\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.501 ns" { clk~clkctrl count[0] } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.87 % ) " "Info: Total cell delay = 1.806 ns ( 64.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.978 ns ( 35.13 % ) " "Info: Total interconnect delay = 0.978 ns ( 35.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clk clk~clkctrl count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clk {} clk~combout {} clk~clkctrl {} count[0] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl count[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} count[25] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clk clk~clkctrl count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clk {} clk~combout {} clk~clkctrl {} count[0] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.808 ns" { count[0] Add0~313 Add0~315 Add0~317 Add0~319 Add0~321 Add0~323 Add0~325 Add0~327 Add0~329 Add0~331 Add0~333 Add0~335 Add0~337 Add0~339 Add0~341 Add0~343 Add0~345 Add0~347 Add0~349 Add0~351 Add0~353 Add0~355 Add0~357 Add0~359 Add0~361 Add0~362 count~282 count[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.808 ns" { count[0] {} Add0~313 {} Add0~315 {} Add0~317 {} Add0~319 {} Add0~321 {} Add0~323 {} Add0~325 {} Add0~327 {} Add0~329 {} Add0~331 {} Add0~333 {} Add0~335 {} Add0~337 {} Add0~339 {} Add0~341 {} Add0~343 {} Add0~345 {} Add0~347 {} Add0~349 {} Add0~351 {} Add0~353 {} Add0~355 {} Add0~357 {} Add0~359 {} Add0~361 {} Add0~362 {} count~282 {} count[25] {} } { 0.000ns 0.472ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.370ns 0.000ns } { 0.000ns 0.621ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.175ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.086ns 0.190ns 0.086ns 0.086ns 0.086ns 0.086ns 0.506ns 0.370ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.788 ns" { clk clk~clkctrl count[25] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.788 ns" { clk {} clk~combout {} clk~clkctrl {} count[25] {} } { 0.000ns 0.000ns 0.143ns 0.839ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.784 ns" { clk clk~clkctrl count[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.784 ns" { clk {} clk~combout {} clk~clkctrl {} count[0] {} } { 0.000ns 0.000ns 0.143ns 0.835ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk QG QG~reg0 8.691 ns register " "Info: tco from clock \"clk\" to destination pin \"QG\" through register \"QG~reg0\" is 8.691 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.803 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.803 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 40 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 40; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.666 ns) 2.803 ns QG~reg0 3 REG LCFF_X19_Y12_N3 1 " "Info: 3: + IC(0.854 ns) + CELL(0.666 ns) = 2.803 ns; Loc. = LCFF_X19_Y12_N3; Fanout = 1; REG Node = 'QG~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.520 ns" { clk~clkctrl QG~reg0 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.43 % ) " "Info: Total cell delay = 1.806 ns ( 64.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.997 ns ( 35.57 % ) " "Info: Total interconnect delay = 0.997 ns ( 35.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.803 ns" { clk clk~clkctrl QG~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.803 ns" { clk {} clk~combout {} clk~clkctrl {} QG~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 30 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.584 ns + Longest register pin " "Info: + Longest register to pin delay is 5.584 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns QG~reg0 1 REG LCFF_X19_Y12_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y12_N3; Fanout = 1; REG Node = 'QG~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { QG~reg0 } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 30 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.488 ns) + CELL(3.096 ns) 5.584 ns QG 2 PIN PIN_8 0 " "Info: 2: + IC(2.488 ns) + CELL(3.096 ns) = 5.584 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'QG'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.584 ns" { QG~reg0 QG } "NODE_NAME" } } { "FPQ.vhd" "" { Text "E:/EDA/SHZ/FPQ.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 55.44 % ) " "Info: Total cell delay = 3.096 ns ( 55.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.488 ns ( 44.56 % ) " "Info: Total interconnect delay = 2.488 ns ( 44.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.584 ns" { QG~reg0 QG } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.584 ns" { QG~reg0 {} QG {} } { 0.000ns 2.488ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.803 ns" { clk clk~clkctrl QG~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.803 ns" { clk {} clk~combout {} clk~clkctrl {} QG~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.854ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.584 ns" { QG~reg0 QG } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.584 ns" { QG~reg0 {} QG {} } { 0.000ns 2.488ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}