prev_cmp_xs.tan.qmsg

基于fpga数字钟系统

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register x\[1\] register x\[2\] 293.08 MHz 3.412 ns Internal " "Info: Clock \"clk\" has Internal fmax of 293.08 MHz between source register \"x\[1\]\" and destination register \"x\[2\]\" (period= 3.412 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.148 ns + Longest register register " "Info: + Longest register to register delay is 3.148 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns x\[1\] 1 REG LCFF_X1_Y3_N21 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N21; Fanout = 4; REG Node = 'x\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { x[1] } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.475 ns) + CELL(0.615 ns) 1.090 ns Add0~207 2 COMB LCCOMB_X1_Y3_N30 3 " "Info: 2: + IC(0.475 ns) + CELL(0.615 ns) = 1.090 ns; Loc. = LCCOMB_X1_Y3_N30; Fanout = 3; COMB Node = 'Add0~207'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.090 ns" { x[1] Add0~207 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.402 ns) + CELL(0.206 ns) 1.698 ns Add0~208 3 COMB LCCOMB_X1_Y3_N14 3 " "Info: 3: + IC(0.402 ns) + CELL(0.206 ns) = 1.698 ns; Loc. = LCCOMB_X1_Y3_N14; Fanout = 3; COMB Node = 'Add0~208'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.608 ns" { Add0~207 Add0~208 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.401 ns) + CELL(0.370 ns) 2.469 ns Equal0~47 4 COMB LCCOMB_X1_Y3_N12 3 " "Info: 4: + IC(0.401 ns) + CELL(0.370 ns) = 2.469 ns; Loc. = LCCOMB_X1_Y3_N12; Fanout = 3; COMB Node = 'Equal0~47'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.771 ns" { Add0~208 Equal0~47 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 3.040 ns x~163 5 COMB LCCOMB_X1_Y3_N24 1 " "Info: 5: + IC(0.365 ns) + CELL(0.206 ns) = 3.040 ns; Loc. = LCCOMB_X1_Y3_N24; Fanout = 1; COMB Node = 'x~163'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { Equal0~47 x~163 } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.148 ns x\[2\] 6 REG LCFF_X1_Y3_N25 3 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 3.148 ns; Loc. = LCFF_X1_Y3_N25; Fanout = 3; REG Node = 'x\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { x~163 x[2] } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.505 ns ( 47.81 % ) " "Info: Total cell delay = 1.505 ns ( 47.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.643 ns ( 52.19 % ) " "Info: Total interconnect delay = 1.643 ns ( 52.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.148 ns" { x[1] Add0~207 Add0~208 Equal0~47 x~163 x[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.148 ns" { x[1] {} Add0~207 {} Add0~208 {} Equal0~47 {} x~163 {} x[2] {} } { 0.000ns 0.475ns 0.402ns 0.401ns 0.365ns 0.000ns } { 0.000ns 0.615ns 0.206ns 0.370ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.779 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 2.779 ns x\[2\] 3 REG LCFF_X1_Y3_N25 3 " "Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N25; Fanout = 3; REG Node = 'x\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.496 ns" { clk~clkctrl x[2] } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.99 % ) " "Info: Total cell delay = 1.806 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.973 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.973 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk clk~clkctrl x[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk {} clk~combout {} clk~clkctrl {} x[2] {} } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.779 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 2.779 ns x\[1\] 3 REG LCFF_X1_Y3_N21 4 " "Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N21; Fanout = 4; REG Node = 'x\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.496 ns" { clk~clkctrl x[1] } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.99 % ) " "Info: Total cell delay = 1.806 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.973 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.973 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk clk~clkctrl x[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk {} clk~combout {} clk~clkctrl {} x[1] {} } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk clk~clkctrl x[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk {} clk~combout {} clk~clkctrl {} x[2] {} } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk clk~clkctrl x[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk {} clk~combout {} clk~clkctrl {} x[1] {} } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.148 ns" { x[1] Add0~207 Add0~208 Equal0~47 x~163 x[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.148 ns" { x[1] {} Add0~207 {} Add0~208 {} Equal0~47 {} x~163 {} x[2] {} } { 0.000ns 0.475ns 0.402ns 0.401ns 0.365ns 0.000ns } { 0.000ns 0.615ns 0.206ns 0.370ns 0.206ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk clk~clkctrl x[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk {} clk~combout {} clk~clkctrl {} x[2] {} } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk clk~clkctrl x[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk {} clk~combout {} clk~clkctrl {} x[1] {} } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk sc sc~reg0 6.903 ns register " "Info: tco from clock \"clk\" to destination pin \"sc\" through register \"sc~reg0\" is 6.903 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.779 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.779 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 7 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 7; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.830 ns) + CELL(0.666 ns) 2.779 ns sc~reg0 3 REG LCFF_X1_Y3_N13 1 " "Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X1_Y3_N13; Fanout = 1; REG Node = 'sc~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.496 ns" { clk~clkctrl sc~reg0 } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.99 % ) " "Info: Total cell delay = 1.806 ns ( 64.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.973 ns ( 35.01 % ) " "Info: Total interconnect delay = 0.973 ns ( 35.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk clk~clkctrl sc~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk {} clk~combout {} clk~clkctrl {} sc~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.820 ns + Longest register pin " "Info: + Longest register to pin delay is 3.820 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sc~reg0 1 REG LCFF_X1_Y3_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y3_N13; Fanout = 1; REG Node = 'sc~reg0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { sc~reg0 } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.704 ns) + CELL(3.116 ns) 3.820 ns sc 2 PIN PIN_43 0 " "Info: 2: + IC(0.704 ns) + CELL(3.116 ns) = 3.820 ns; Loc. = PIN_43; Fanout = 0; PIN Node = 'sc'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.820 ns" { sc~reg0 sc } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.116 ns ( 81.57 % ) " "Info: Total cell delay = 3.116 ns ( 81.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.704 ns ( 18.43 % ) " "Info: Total interconnect delay = 0.704 ns ( 18.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.820 ns" { sc~reg0 sc } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.820 ns" { sc~reg0 {} sc {} } { 0.000ns 0.704ns } { 0.000ns 3.116ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.779 ns" { clk clk~clkctrl sc~reg0 } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.779 ns" { clk {} clk~combout {} clk~clkctrl {} sc~reg0 {} } { 0.000ns 0.000ns 0.143ns 0.830ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.820 ns" { sc~reg0 sc } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.820 ns" { sc~reg0 {} sc {} } { 0.000ns 0.704ns } { 0.000ns 3.116ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 17:17:26 2008 " "Info: Processing ended: Fri Nov 28 17:17:26 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}