📄 prev_cmp_clock.tan.qmsg

📁 基于fpga数字钟系统
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register mminite1\[3\] register mhour22\[1\] 174.95 MHz 5.716 ns Internal " "Info: Clock \"clk\" has Internal fmax of 174.95 MHz between source register \"mminite1\[3\]\" and destination register \"mhour22\[1\]\" (period= 5.716 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.452 ns + Longest register register " "Info: + Longest register to register delay is 5.452 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mminite1\[3\] 1 REG LCFF_X24_Y8_N19 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y8_N19; Fanout = 4; REG Node = 'mminite1\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mminite1[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.961 ns) + CELL(0.651 ns) 2.612 ns Equal3~44 2 COMB LCCOMB_X25_Y8_N20 2 " "Info: 2: + IC(1.961 ns) + CELL(0.651 ns) = 2.612 ns; Loc. = LCCOMB_X25_Y8_N20; Fanout = 2; COMB Node = 'Equal3~44'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.612 ns" { mminite1[3] Equal3~44 } "NODE_NAME" } } { "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/72/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.377 ns) + CELL(0.370 ns) 3.359 ns mhour22~1957 3 COMB LCCOMB_X25_Y8_N18 5 " "Info: 3: + IC(0.377 ns) + CELL(0.370 ns) = 3.359 ns; Loc. = LCCOMB_X25_Y8_N18; Fanout = 5; COMB Node = 'mhour22~1957'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.747 ns" { Equal3~44 mhour22~1957 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.412 ns) + CELL(0.589 ns) 4.360 ns mhour22~1966 4 COMB LCCOMB_X25_Y8_N4 1 " "Info: 4: + IC(0.412 ns) + CELL(0.589 ns) = 4.360 ns; Loc. = LCCOMB_X25_Y8_N4; Fanout = 1; COMB Node = 'mhour22~1966'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.001 ns" { mhour22~1957 mhour22~1966 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.368 ns) + CELL(0.616 ns) 5.344 ns mhour22~1968 5 COMB LCCOMB_X25_Y8_N26 1 " "Info: 5: + IC(0.368 ns) + CELL(0.616 ns) = 5.344 ns; Loc. = LCCOMB_X25_Y8_N26; Fanout = 1; COMB Node = 'mhour22~1968'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.984 ns" { mhour22~1966 mhour22~1968 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 5.452 ns mhour22\[1\] 6 REG LCFF_X25_Y8_N27 11 " "Info: 6: + IC(0.000 ns) + CELL(0.108 ns) = 5.452 ns; Loc. = LCFF_X25_Y8_N27; Fanout = 11; REG Node = 'mhour22\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { mhour22~1968 mhour22[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.334 ns ( 42.81 % ) " "Info: Total cell delay = 2.334 ns ( 42.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.118 ns ( 57.19 % ) " "Info: Total interconnect delay = 3.118 ns ( 57.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.452 ns" { mminite1[3] Equal3~44 mhour22~1957 mhour22~1966 mhour22~1968 mhour22[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.452 ns" { mminite1[3] {} Equal3~44 {} mhour22~1957 {} mhour22~1966 {} mhour22~1968 {} mhour22[1] {} } { 0.000ns 1.961ns 0.377ns 0.412ns 0.368ns 0.000ns } { 0.000ns 0.651ns 0.370ns 0.589ns 0.616ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.791 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.666 ns) 2.791 ns mhour22\[1\] 3 REG LCFF_X25_Y8_N27 11 " "Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.791 ns; Loc. = LCFF_X25_Y8_N27; Fanout = 11; REG Node = 'mhour22\[1\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { clk~clkctrl mhour22[1] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.71 % ) " "Info: Total cell delay = 1.806 ns ( 64.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.985 ns ( 35.29 % ) " "Info: Total interconnect delay = 0.985 ns ( 35.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mhour22[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mhour22[1] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.791 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.666 ns) 2.791 ns mminite1\[3\] 3 REG LCFF_X24_Y8_N19 4 " "Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.791 ns; Loc. = LCFF_X24_Y8_N19; Fanout = 4; REG Node = 'mminite1\[3\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { clk~clkctrl mminite1[3] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.71 % ) " "Info: Total cell delay = 1.806 ns ( 64.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.985 ns ( 35.29 % ) " "Info: Total interconnect delay = 0.985 ns ( 35.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mminite1[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mminite1[3] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mhour22[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mhour22[1] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mminite1[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mminite1[3] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.452 ns" { mminite1[3] Equal3~44 mhour22~1957 mhour22~1966 mhour22~1968 mhour22[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.452 ns" { mminite1[3] {} Equal3~44 {} mhour22~1957 {} mhour22~1966 {} mhour22~1968 {} mhour22[1] {} } { 0.000ns 1.961ns 0.377ns 0.412ns 0.368ns 0.000ns } { 0.000ns 0.651ns 0.370ns 0.589ns 0.616ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mhour22[1] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mhour22[1] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mminite1[3] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mminite1[3] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "mhour22\[2\] s3 clk 7.364 ns register " "Info: tsu for register \"mhour22\[2\]\" (data pin = \"s3\", clock pin = \"clk\") is 7.364 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.195 ns + Longest pin register " "Info: + Longest pin to register delay is 10.195 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.984 ns) 0.984 ns s3 1 PIN PIN_160 2 " "Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_160; Fanout = 2; PIN Node = 's3'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { s3 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.259 ns) + CELL(0.370 ns) 7.613 ns mhour22~1959 2 COMB LCCOMB_X26_Y8_N26 8 " "Info: 2: + IC(6.259 ns) + CELL(0.370 ns) = 7.613 ns; Loc. = LCCOMB_X26_Y8_N26; Fanout = 8; COMB Node = 'mhour22~1959'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.629 ns" { s3 mhour22~1959 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.095 ns) + CELL(0.370 ns) 9.078 ns mhour22~1975 3 COMB LCCOMB_X26_Y8_N18 1 " "Info: 3: + IC(1.095 ns) + CELL(0.370 ns) = 9.078 ns; Loc. = LCCOMB_X26_Y8_N18; Fanout = 1; COMB Node = 'mhour22~1975'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.465 ns" { mhour22~1959 mhour22~1975 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.385 ns) + CELL(0.624 ns) 10.087 ns mhour22~1969 4 COMB LCCOMB_X26_Y8_N0 1 " "Info: 4: + IC(0.385 ns) + CELL(0.624 ns) = 10.087 ns; Loc. = LCCOMB_X26_Y8_N0; Fanout = 1; COMB Node = 'mhour22~1969'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.009 ns" { mhour22~1975 mhour22~1969 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 10.195 ns mhour22\[2\] 5 REG LCFF_X26_Y8_N1 7 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 10.195 ns; Loc. = LCFF_X26_Y8_N1; Fanout = 7; REG Node = 'mhour22\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { mhour22~1969 mhour22[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.456 ns ( 24.09 % ) " "Info: Total cell delay = 2.456 ns ( 24.09 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.739 ns ( 75.91 % ) " "Info: Total interconnect delay = 7.739 ns ( 75.91 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.195 ns" { s3 mhour22~1959 mhour22~1975 mhour22~1969 mhour22[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.195 ns" { s3 {} s3~combout {} mhour22~1959 {} mhour22~1975 {} mhour22~1969 {} mhour22[2] {} } { 0.000ns 0.000ns 6.259ns 1.095ns 0.385ns 0.000ns } { 0.000ns 0.984ns 0.370ns 0.370ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.791 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.666 ns) 2.791 ns mhour22\[2\] 3 REG LCFF_X26_Y8_N1 7 " "Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.791 ns; Loc. = LCFF_X26_Y8_N1; Fanout = 7; REG Node = 'mhour22\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { clk~clkctrl mhour22[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.71 % ) " "Info: Total cell delay = 1.806 ns ( 64.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.985 ns ( 35.29 % ) " "Info: Total interconnect delay = 0.985 ns ( 35.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mhour22[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mhour22[2] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "10.195 ns" { s3 mhour22~1959 mhour22~1975 mhour22~1969 mhour22[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "10.195 ns" { s3 {} s3~combout {} mhour22~1959 {} mhour22~1975 {} mhour22~1969 {} mhour22[2] {} } { 0.000ns 0.000ns 6.259ns 1.095ns 0.385ns 0.000ns } { 0.000ns 0.984ns 0.370ns 0.370ns 0.624ns 0.108ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mhour22[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mhour22[2] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk minite2\[0\] mminite2\[0\] 8.317 ns register " "Info: tco from clock \"clk\" to destination pin \"minite2\[0\]\" through register \"mminite2\[0\]\" is 8.317 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.791 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.666 ns) 2.791 ns mminite2\[0\] 3 REG LCFF_X24_Y8_N27 6 " "Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.791 ns; Loc. = LCFF_X24_Y8_N27; Fanout = 6; REG Node = 'mminite2\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { clk~clkctrl mminite2[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.71 % ) " "Info: Total cell delay = 1.806 ns ( 64.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.985 ns ( 35.29 % ) " "Info: Total interconnect delay = 0.985 ns ( 35.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mminite2[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mminite2[0] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.222 ns + Longest register pin " "Info: + Longest register to pin delay is 5.222 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns mminite2\[0\] 1 REG LCFF_X24_Y8_N27 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X24_Y8_N27; Fanout = 6; REG Node = 'mminite2\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { mminite2[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.126 ns) + CELL(3.096 ns) 5.222 ns minite2\[0\] 2 PIN PIN_134 0 " "Info: 2: + IC(2.126 ns) + CELL(3.096 ns) = 5.222 ns; Loc. = PIN_134; Fanout = 0; PIN Node = 'minite2\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.222 ns" { mminite2[0] minite2[0] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 59.29 % ) " "Info: Total cell delay = 3.096 ns ( 59.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.126 ns ( 40.71 % ) " "Info: Total interconnect delay = 2.126 ns ( 40.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.222 ns" { mminite2[0] minite2[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.222 ns" { mminite2[0] {} minite2[0] {} } { 0.000ns 2.126ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mminite2[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mminite2[0] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.222 ns" { mminite2[0] minite2[0] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "5.222 ns" { mminite2[0] {} minite2[0] {} } { 0.000ns 2.126ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "mhour11\[2\] set clk -0.775 ns register " "Info: th for register \"mhour11\[2\]\" (data pin = \"set\", clock pin = \"clk\") is -0.775 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.791 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.791 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk 1 CLK PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.143 ns) + CELL(0.000 ns) 1.283 ns clk~clkctrl 2 COMB CLKCTRL_G2 24 " "Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 24; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.143 ns" { clk clk~clkctrl } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.842 ns) + CELL(0.666 ns) 2.791 ns mhour11\[2\] 3 REG LCFF_X26_Y8_N5 6 " "Info: 3: + IC(0.842 ns) + CELL(0.666 ns) = 2.791 ns; Loc. = LCFF_X26_Y8_N5; Fanout = 6; REG Node = 'mhour11\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.508 ns" { clk~clkctrl mhour11[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 64.71 % ) " "Info: Total cell delay = 1.806 ns ( 64.71 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.985 ns ( 35.29 % ) " "Info: Total interconnect delay = 0.985 ns ( 35.29 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mhour11[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mhour11[2] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.306 ns + " "Info: + Micro hold delay of destination is 0.306 ns" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.872 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.872 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns set 1 PIN PIN_27 10 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_27; Fanout = 10; PIN Node = 'set'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { set } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.624 ns) 3.764 ns mhour11~508 2 COMB LCCOMB_X26_Y8_N4 1 " "Info: 2: + IC(2.000 ns) + CELL(0.624 ns) = 3.764 ns; Loc. = LCCOMB_X26_Y8_N4; Fanout = 1; COMB Node = 'mhour11~508'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.624 ns" { set mhour11~508 } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 3.872 ns mhour11\[2\] 3 REG LCFF_X26_Y8_N5 6 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 3.872 ns; Loc. = LCFF_X26_Y8_N5; Fanout = 6; REG Node = 'mhour11\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { mhour11~508 mhour11[2] } "NODE_NAME" } } { "clock.vhd" "" { Text "E:/EDA/SHZ/clock.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.872 ns ( 48.35 % ) " "Info: Total cell delay = 1.872 ns ( 48.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.65 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.872 ns" { set mhour11~508 mhour11[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.872 ns" { set {} set~combout {} mhour11~508 {} mhour11[2] {} } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 1.140ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.791 ns" { clk clk~clkctrl mhour11[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.791 ns" { clk {} clk~combout {} clk~clkctrl {} mhour11[2] {} } { 0.000ns 0.000ns 0.143ns 0.842ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.872 ns" { set mhour11~508 mhour11[2] } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.872 ns" { set {} set~combout {} mhour11~508 {} mhour11[2] {} } { 0.000ns 0.000ns 2.000ns 0.000ns } { 0.000ns 1.140ns 0.624ns 0.108ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
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