xs.tan.qmsg

基于fpga数字钟系统

{ "Info" "ITDB_TSU_RESULT" "y clk a1\[0\] 6.179 ns register " "Info: tsu for register \"y\" (data pin = \"clk\", clock pin = \"a1\[0\]\") is 6.179 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.867 ns + Longest pin register " "Info: + Longest pin to register delay is 7.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.014 ns) 1.014 ns clk 1 PIN PIN_207 1 " "Info: 1: + IC(0.000 ns) + CELL(1.014 ns) = 1.014 ns; Loc. = PIN_207; Fanout = 1; PIN Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.203 ns) + CELL(0.650 ns) 7.867 ns y 2 REG LCCOMB_X1_Y5_N22 1 " "Info: 2: + IC(6.203 ns) + CELL(0.650 ns) = 7.867 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk y } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.664 ns ( 21.15 % ) " "Info: Total cell delay = 1.664 ns ( 21.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.203 ns ( 78.85 % ) " "Info: Total interconnect delay = 6.203 ns ( 78.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.867 ns" { clk y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.867 ns" { clk {} clk~combout {} y {} } { 0.000ns 0.000ns 6.203ns } { 0.000ns 1.014ns 0.650ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.203 ns + " "Info: + Micro setup delay of destination is 1.203 ns" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a1\[0\] destination 2.891 ns - Shortest register " "Info: - Shortest clock path from clock \"a1\[0\]\" to destination register is 2.891 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.985 ns) 0.985 ns a1\[0\] 1 CLK PIN_30 1 " "Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_30; Fanout = 1; CLK Node = 'a1\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1[0] } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.968 ns) + CELL(0.370 ns) 2.323 ns process0~0 2 COMB LCCOMB_X1_Y5_N0 1 " "Info: 2: + IC(0.968 ns) + CELL(0.370 ns) = 2.323 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 1; COMB Node = 'process0~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.338 ns" { a1[0] process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 2.891 ns y 3 REG LCCOMB_X1_Y5_N22 1 " "Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 2.891 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { process0~0 y } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.561 ns ( 54.00 % ) " "Info: Total cell delay = 1.561 ns ( 54.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.330 ns ( 46.00 % ) " "Info: Total interconnect delay = 1.330 ns ( 46.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.891 ns" { a1[0] process0~0 y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.891 ns" { a1[0] {} a1[0]~combout {} process0~0 {} y {} } { 0.000ns 0.000ns 0.968ns 0.362ns } { 0.000ns 0.985ns 0.370ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.867 ns" { clk y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.867 ns" { clk {} clk~combout {} y {} } { 0.000ns 0.000ns 6.203ns } { 0.000ns 1.014ns 0.650ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.891 ns" { a1[0] process0~0 y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.891 ns" { a1[0] {} a1[0]~combout {} process0~0 {} y {} } { 0.000ns 0.000ns 0.968ns 0.362ns } { 0.000ns 0.985ns 0.370ns 0.206ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "a1\[2\] sc y 7.948 ns register " "Info: tco from clock \"a1\[2\]\" to destination pin \"sc\" through register \"y\" is 7.948 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a1\[2\] source 3.798 ns + Longest register " "Info: + Longest clock path from clock \"a1\[2\]\" to source register is 3.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns a1\[2\] 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'a1\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1[2] } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.621 ns) + CELL(0.614 ns) 3.230 ns process0~0 2 COMB LCCOMB_X1_Y5_N0 1 " "Info: 2: + IC(1.621 ns) + CELL(0.614 ns) = 3.230 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 1; COMB Node = 'process0~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.235 ns" { a1[2] process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 3.798 ns y 3 REG LCCOMB_X1_Y5_N22 1 " "Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 3.798 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { process0~0 y } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.815 ns ( 47.79 % ) " "Info: Total cell delay = 1.815 ns ( 47.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.983 ns ( 52.21 % ) " "Info: Total interconnect delay = 1.983 ns ( 52.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.798 ns" { a1[2] process0~0 y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.798 ns" { a1[2] {} a1[2]~combout {} process0~0 {} y {} } { 0.000ns 0.000ns 1.621ns 0.362ns } { 0.000ns 0.995ns 0.614ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.150 ns + Longest register pin " "Info: + Longest register to pin delay is 4.150 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns y 1 REG LCCOMB_X1_Y5_N22 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { y } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.054 ns) + CELL(3.096 ns) 4.150 ns sc 2 PIN PIN_34 0 " "Info: 2: + IC(1.054 ns) + CELL(3.096 ns) = 4.150 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'sc'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.150 ns" { y sc } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.096 ns ( 74.60 % ) " "Info: Total cell delay = 3.096 ns ( 74.60 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.054 ns ( 25.40 % ) " "Info: Total interconnect delay = 1.054 ns ( 25.40 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.150 ns" { y sc } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.150 ns" { y {} sc {} } { 0.000ns 1.054ns } { 0.000ns 3.096ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.798 ns" { a1[2] process0~0 y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.798 ns" { a1[2] {} a1[2]~combout {} process0~0 {} y {} } { 0.000ns 0.000ns 1.621ns 0.362ns } { 0.000ns 0.995ns 0.614ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.150 ns" { y sc } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.150 ns" { y {} sc {} } { 0.000ns 1.054ns } { 0.000ns 3.096ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "y clk a1\[2\] -4.069 ns register " "Info: th for register \"y\" (data pin = \"clk\", clock pin = \"a1\[2\]\") is -4.069 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "a1\[2\] destination 3.798 ns + Longest register " "Info: + Longest clock path from clock \"a1\[2\]\" to destination register is 3.798 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.995 ns) 0.995 ns a1\[2\] 1 CLK PIN_12 1 " "Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'a1\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { a1[2] } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.621 ns) + CELL(0.614 ns) 3.230 ns process0~0 2 COMB LCCOMB_X1_Y5_N0 1 " "Info: 2: + IC(1.621 ns) + CELL(0.614 ns) = 3.230 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 1; COMB Node = 'process0~0'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.235 ns" { a1[2] process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.362 ns) + CELL(0.206 ns) 3.798 ns y 3 REG LCCOMB_X1_Y5_N22 1 " "Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 3.798 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.568 ns" { process0~0 y } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.815 ns ( 47.79 % ) " "Info: Total cell delay = 1.815 ns ( 47.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.983 ns ( 52.21 % ) " "Info: Total interconnect delay = 1.983 ns ( 52.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.798 ns" { a1[2] process0~0 y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.798 ns" { a1[2] {} a1[2]~combout {} process0~0 {} y {} } { 0.000ns 0.000ns 1.621ns 0.362ns } { 0.000ns 0.995ns 0.614ns 0.206ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.867 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.867 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.014 ns) 1.014 ns clk 1 PIN PIN_207 1 " "Info: 1: + IC(0.000 ns) + CELL(1.014 ns) = 1.014 ns; Loc. = PIN_207; Fanout = 1; PIN Node = 'clk'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.203 ns) + CELL(0.650 ns) 7.867 ns y 2 REG LCCOMB_X1_Y5_N22 1 " "Info: 2: + IC(6.203 ns) + CELL(0.650 ns) = 7.867 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.853 ns" { clk y } "NODE_NAME" } } { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.664 ns ( 21.15 % ) " "Info: Total cell delay = 1.664 ns ( 21.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.203 ns ( 78.85 % ) " "Info: Total interconnect delay = 6.203 ns ( 78.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.867 ns" { clk y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.867 ns" { clk {} clk~combout {} y {} } { 0.000ns 0.000ns 6.203ns } { 0.000ns 1.014ns 0.650ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.798 ns" { a1[2] process0~0 y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "3.798 ns" { a1[2] {} a1[2]~combout {} process0~0 {} y {} } { 0.000ns 0.000ns 1.621ns 0.362ns } { 0.000ns 0.995ns 0.614ns 0.206ns } "" } } { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "7.867 ns" { clk y } "NODE_NAME" } } { "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/72/quartus/bin/Technology_Viewer.qrui" "7.867 ns" { clk {} clk~combout {} y {} } { 0.000ns 0.000ns 6.203ns } { 0.000ns 1.014ns 0.650ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Nov 28 21:18:08 2008 " "Info: Processing ended: Fri Nov 28 21:18:08 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}