prev_cmp_seltime.qmsg

基于fpga数字钟系统

{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/EDA/SHZ/seltime.fit.smsg " "Info: Generated suppressed messages file E:/EDA/SHZ/seltime.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "176 " "Info: Allocated 176 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 27 18:15:56 2008 " "Info: Processing ended: Thu Nov 27 18:15:56 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 27 18:15:57 2008 " "Info: Processing started: Thu Nov 27 18:15:57 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off seltime -c seltime " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off seltime -c seltime" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 27 18:15:59 2008 " "Info: Processing ended: Thu Nov 27 18:15:59 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 27 18:16:00 2008 " "Info: Processing started: Thu Nov 27 18:16:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off seltime -c seltime --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off seltime -c seltime --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "daout\[0\]\$latch " "Warning: Node \"daout\[0\]\$latch\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "daout\[1\]\$latch " "Warning: Node \"daout\[1\]\$latch\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "daout\[2\]\$latch " "Warning: Node \"daout\[2\]\$latch\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "daout\[3\]\$latch " "Warning: Node \"daout\[3\]\$latch\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "dp\$latch " "Warning: Node \"dp\$latch\" is a latch" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 17 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk1 " "Info: Assuming node \"clk1\" is an undefined clock" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 8 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux6~18 " "Info: Detected gated clock \"Mux6~18\" as buffer" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 26 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux6~18" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count\[1\] " "Info: Detected ripple clock \"count\[1\]\" as buffer" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count\[2\] " "Info: Detected ripple clock \"count\[2\]\" as buffer" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } } { "c:/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk1 register register count\[0\] count\[2\] 360.1 MHz Internal " "Info: Clock \"clk1\" Internal fmax is restricted to 360.1 MHz between source register \"count\[0\]\" and destination register \"count\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.777 ns " "Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.223 ns + Longest register register " "Info: + Longest register to register delay is 1.223 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[0\] 1 REG LCFF_X12_Y10_N13 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y10_N13; Fanout = 11; REG Node = 'count\[0\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[0] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.509 ns) + CELL(0.606 ns) 1.115 ns count~151 2 COMB LCCOMB_X12_Y10_N4 1 " "Info: 2: + IC(0.509 ns) + CELL(0.606 ns) = 1.115 ns; Loc. = LCCOMB_X12_Y10_N4; Fanout = 1; COMB Node = 'count~151'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.115 ns" { count[0] count~151 } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 1.223 ns count\[2\] 3 REG LCFF_X12_Y10_N5 11 " "Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.223 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count\[2\]'" {  } { { "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { count~151 count[2] } "NODE_NAME" } } { "seltime.vhd" "" { Text "E:/EDA/SHZ/seltime.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.714 ns ( 58.38 % ) " "Info: Total cell delay = 0.714 ns ( 58.38 % )" {  } {  } 0 0 "Total cell delay = %1!s