prev_cmp_tm.map.qmsg

基于fpga数字钟系统

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "daout\[3\] seltime.vhd(17) " "Info (10041): Inferred latch for \"daout\[3\]\" at seltime.vhd(17)" {  } { { "seltime.vhd" "" { Text "E:/EDA/SHZbeifeng/seltime.vhd" 17 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "FPQ.vhd 2 1 " "Warning: Using design file FPQ.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 FPQ-cc " "Info: Found design unit 1: FPQ-cc" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 FPQ " "Info: Found entity 1: FPQ" {  } { { "FPQ.vhd" "" { Text "E:/EDA/SHZbeifeng/FPQ.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FPQ FPQ:inst6 " "Info: Elaborating entity \"FPQ\" for hierarchy \"FPQ:inst6\"" {  } { { "TM.bdf" "inst6" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 32 200 296 128 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "clock.vhd 2 1 " "Warning: Using design file clock.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 clock-one " "Info: Found design unit 1: clock-one" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 9 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 clock " "Info: Found entity 1: clock" {  } { { "clock.vhd" "" { Text "E:/EDA/SHZbeifeng/clock.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock clock:inst " "Info: Elaborating entity \"clock\" for hierarchy \"clock:inst\"" {  } { { "TM.bdf" "inst" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 48 392 528 208 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "XS XS:inst1 " "Info: Elaborating entity \"XS\" for hierarchy \"XS:inst1\"" {  } { { "TM.bdf" "inst1" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 232 392 488 328 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "clk XS.vhd(25) " "Warning (10492): VHDL Process Statement warning at XS.vhd(25): signal \"clk\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 25 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "y XS.vhd(11) " "Warning (10631): VHDL Process Statement warning at XS.vhd(11): inferring latch(es) for signal or variable \"y\", which holds its previous value in one or more paths through the process" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 11 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "y XS.vhd(15) " "Info (10041): Inferred latch for \"y\" at XS.vhd(15)" {  } { { "XS.vhd" "" { Text "E:/EDA/SHZbeifeng/XS.vhd" 15 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "deled deled:inst4 " "Info: Elaborating entity \"deled\" for hierarchy \"deled:inst4\"" {  } { { "TM.bdf" "inst4" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 48 872 1016 144 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "led\[0\] deled.vhd(10) " "Info (10041): Inferred latch for \"led\[0\]\" at deled.vhd(10)" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "led\[1\] deled.vhd(10) " "Info (10041): Inferred latch for \"led\[1\]\" at deled.vhd(10)" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "led\[2\] deled.vhd(10) " "Info (10041): Inferred latch for \"led\[2\]\" at deled.vhd(10)" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "led\[3\] deled.vhd(10) " "Info (10041): Inferred latch for \"led\[3\]\" at deled.vhd(10)" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "led\[4\] deled.vhd(10) " "Info (10041): Inferred latch for \"led\[4\]\" at deled.vhd(10)" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "led\[5\] deled.vhd(10) " "Info (10041): Inferred latch for \"led\[5\]\" at deled.vhd(10)" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "led\[6\] deled.vhd(10) " "Info (10041): Inferred latch for \"led\[6\]\" at deled.vhd(10)" {  } { { "deled.vhd" "" { Text "E:/EDA/SHZbeifeng/deled.vhd" 10 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "YIMA.vhd 2 1 " "Warning: Using design file YIMA.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 YIMA-baby " "Info: Found design unit 1: YIMA-baby" {  } { { "YIMA.vhd" "" { Text "E:/EDA/SHZbeifeng/YIMA.vhd" 7 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 YIMA " "Info: Found entity 1: YIMA" {  } { { "YIMA.vhd" "" { Text "E:/EDA/SHZbeifeng/YIMA.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "YIMA YIMA:inst3 " "Info: Elaborating entity \"YIMA\" for hierarchy \"YIMA:inst3\"" {  } { { "TM.bdf" "inst3" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 184 872 992 280 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Error" "ESGN_NON_EXISTENT_PORT" "en inst1 " "Error: Port \"en\" does not exist in macrofunction \"inst1\"" {  } { { "TM.bdf" "inst1" { Schematic "E:/EDA/SHZbeifeng/TM.bdf" { { 232 392 488 328 "inst1" "" } } } }  } 0 0 "Port \"%1!s!\" does not exist in macrofunction \"%2!s!\"" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  15 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "157 " "Info: Allocated 157 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Fri Nov 28 21:16:17 2008 " "Error: Processing ended: Fri Nov 28 21:16:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}