tm.qsf

基于fpga数字钟系统

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		TM_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C5Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY TM
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:18:10  NOVEMBER 27, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 7.2
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name SOURCE_FILE TM
set_global_assignment -name BDF_FILE TM.bdf
set_global_assignment -name VHDL_FILE deled.vhd
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition -to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_location_assignment PIN_23 -to CLK
set_location_assignment PIN_118 -to h
set_location_assignment PIN_97 -to K0
set_location_assignment PIN_99 -to K1
set_location_assignment PIN_95 -to K2
set_location_assignment PIN_96 -to K3
set_location_assignment PIN_133 -to led[6]
set_location_assignment PIN_127 -to led[5]
set_location_assignment PIN_116 -to led[4]
set_location_assignment PIN_117 -to led[3]
set_location_assignment PIN_128 -to led[2]
set_location_assignment PIN_134 -to led[1]
set_location_assignment PIN_115 -to led[0]
set_location_assignment PIN_143 -to yma[7]
set_location_assignment PIN_144 -to yma[6]
set_location_assignment PIN_141 -to yma[5]
set_location_assignment PIN_142 -to yma[4]
set_location_assignment PIN_138 -to yma[3]
set_location_assignment PIN_139 -to yma[2]
set_location_assignment PIN_135 -to yma[1]
set_location_assignment PIN_137 -to yma[0]
set_global_assignment -name VHDL_FILE XS.vhd
set_location_assignment PIN_152 -to fenm