clock.map.summary

基于fpga数字钟系统

Analysis & Synthesis Status : Successful - Fri Nov 28 16:20:25 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : Cyclone II
Total logic elements : 47
    Total combinational functions : 47
    Dedicated logic registers : 22
Total registers : 22
Total pins : 30
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0