seltime.tan.rpt

基于fpga数字钟系统

    Warning: Node "daout[0]$latch" is a latch
    Warning: Node "daout[1]$latch" is a latch
    Warning: Node "daout[2]$latch" is a latch
    Warning: Node "daout[3]$latch" is a latch
    Warning: Node "dp$latch" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk1" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected gated clock "Mux6~18" as buffer
    Info: Detected ripple clock "count[1]" as buffer
    Info: Detected ripple clock "count[2]" as buffer
Info: Clock "clk1" Internal fmax is restricted to 360.1 MHz between source register "count[0]" and destination register "count[2]"
    Info: fmax restricted to clock pin edge rate 2.777 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.223 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y10_N13; Fanout = 11; REG Node = 'count[0]'
            Info: 2: + IC(0.509 ns) + CELL(0.606 ns) = 1.115 ns; Loc. = LCCOMB_X12_Y10_N4; Fanout = 1; COMB Node = 'count~151'
            Info: 3: + IC(0.000 ns) + CELL(0.108 ns) = 1.223 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count[2]'
            Info: Total cell delay = 0.714 ns ( 58.38 % )
            Info: Total interconnect delay = 0.509 ns ( 41.62 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk1" to destination register is 2.999 ns
                Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'
                Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.999 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count[2]'
                Info: Total cell delay = 1.650 ns ( 55.02 % )
                Info: Total interconnect delay = 1.349 ns ( 44.98 % )
            Info: - Longest clock path from clock "clk1" to source register is 2.999 ns
                Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'
                Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.999 ns; Loc. = LCFF_X12_Y10_N13; Fanout = 11; REG Node = 'count[0]'
                Info: Total cell delay = 1.650 ns ( 55.02 % )
                Info: Total interconnect delay = 1.349 ns ( 44.98 % )
        Info: + Micro clock to output delay of source is 0.304 ns
        Info: + Micro setup delay of destination is -0.040 ns
Warning: Circuit may not operate. Detected 15 non-operational path(s) clocked by clock "clk1" with clock skew larger than data delay. See Compilation Report for details.
Info: Found hold time violation between source  pin or register "count[1]" and destination pin or register "daout[3]$latch" for clock "clk1" (Hold time is 3.718 ns)
    Info: + Largest clock skew is 5.813 ns
        Info: + Longest clock path from clock "clk1" to destination register is 8.812 ns
            Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'
            Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.303 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count[2]'
            Info: 3: + IC(0.811 ns) + CELL(0.624 ns) = 4.738 ns; Loc. = LCCOMB_X13_Y10_N0; Fanout = 1; COMB Node = 'Mux6~18'
            Info: 4: + IC(2.535 ns) + CELL(0.000 ns) = 7.273 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'Mux6~18clkctrl'
            Info: 5: + IC(1.333 ns) + CELL(0.206 ns) = 8.812 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; REG Node = 'daout[3]$latch'
            Info: Total cell delay = 2.784 ns ( 31.59 % )
            Info: Total interconnect delay = 6.028 ns ( 68.41 % )
        Info: - Shortest clock path from clock "clk1" to source register is 2.999 ns
            Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'
            Info: 2: + IC(1.349 ns) + CELL(0.666 ns) = 2.999 ns; Loc. = LCFF_X12_Y10_N31; Fanout = 12; REG Node = 'count[1]'
            Info: Total cell delay = 1.650 ns ( 55.02 % )
            Info: Total interconnect delay = 1.349 ns ( 44.98 % )
    Info: - Micro clock to output delay of source is 0.304 ns
    Info: - Shortest register to register delay is 1.791 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y10_N31; Fanout = 12; REG Node = 'count[1]'
        Info: 2: + IC(0.690 ns) + CELL(0.366 ns) = 1.056 ns; Loc. = LCCOMB_X13_Y10_N8; Fanout = 1; COMB Node = 'Mux5~195'
        Info: 3: + IC(0.365 ns) + CELL(0.370 ns) = 1.791 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; REG Node = 'daout[3]$latch'
        Info: Total cell delay = 0.736 ns ( 41.09 % )
        Info: Total interconnect delay = 1.055 ns ( 58.91 % )
    Info: + Micro hold delay of destination is 0.000 ns
Info: tsu for register "daout[2]$latch" (data pin = "min0[2]", clock pin = "clk1") is 3.848 ns
    Info: + Longest pin to register delay is 11.070 ns
        Info: 1: + IC(0.000 ns) + CELL(1.004 ns) = 1.004 ns; Loc. = PIN_206; Fanout = 1; PIN Node = 'min0[2]'
        Info: 2: + IC(6.839 ns) + CELL(0.651 ns) = 8.494 ns; Loc. = LCCOMB_X12_Y10_N22; Fanout = 1; COMB Node = 'Mux4~193'
        Info: 3: + IC(0.361 ns) + CELL(0.206 ns) = 9.061 ns; Loc. = LCCOMB_X12_Y10_N10; Fanout = 1; COMB Node = 'Mux4~194'
        Info: 4: + IC(0.387 ns) + CELL(0.206 ns) = 9.654 ns; Loc. = LCCOMB_X12_Y10_N2; Fanout = 1; COMB Node = 'Mux4~196'
        Info: 5: + IC(1.046 ns) + CELL(0.370 ns) = 11.070 ns; Loc. = LCCOMB_X10_Y10_N0; Fanout = 1; REG Node = 'daout[2]$latch'
        Info: Total cell delay = 2.437 ns ( 22.01 % )
        Info: Total interconnect delay = 8.633 ns ( 77.99 % )
    Info: + Micro setup delay of destination is 1.197 ns
    Info: - Shortest clock path from clock "clk1" to destination register is 8.419 ns
        Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'
        Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.303 ns; Loc. = LCFF_X12_Y10_N31; Fanout = 12; REG Node = 'count[1]'
        Info: 3: + IC(0.691 ns) + CELL(0.370 ns) = 4.364 ns; Loc. = LCCOMB_X13_Y10_N0; Fanout = 1; COMB Node = 'Mux6~18'
        Info: 4: + IC(2.535 ns) + CELL(0.000 ns) = 6.899 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'Mux6~18clkctrl'
        Info: 5: + IC(1.314 ns) + CELL(0.206 ns) = 8.419 ns; Loc. = LCCOMB_X10_Y10_N0; Fanout = 1; REG Node = 'daout[2]$latch'
        Info: Total cell delay = 2.530 ns ( 30.05 % )
        Info: Total interconnect delay = 5.889 ns ( 69.95 % )
Info: tco from clock "clk1" to destination pin "dp" through register "dp$latch" is 14.304 ns
    Info: + Longest clock path from clock "clk1" to source register is 8.812 ns
        Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'
        Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.303 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count[2]'
        Info: 3: + IC(0.811 ns) + CELL(0.624 ns) = 4.738 ns; Loc. = LCCOMB_X13_Y10_N0; Fanout = 1; COMB Node = 'Mux6~18'
        Info: 4: + IC(2.535 ns) + CELL(0.000 ns) = 7.273 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'Mux6~18clkctrl'
        Info: 5: + IC(1.333 ns) + CELL(0.206 ns) = 8.812 ns; Loc. = LCCOMB_X13_Y10_N24; Fanout = 1; REG Node = 'dp$latch'
        Info: Total cell delay = 2.784 ns ( 31.59 % )
        Info: Total interconnect delay = 6.028 ns ( 68.41 % )
    Info: + Micro clock to output delay of source is 0.000 ns
    Info: + Longest register to pin delay is 5.492 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X13_Y10_N24; Fanout = 1; REG Node = 'dp$latch'
        Info: 2: + IC(2.206 ns) + CELL(3.286 ns) = 5.492 ns; Loc. = PIN_68; Fanout = 0; PIN Node = 'dp'
        Info: Total cell delay = 3.286 ns ( 59.83 % )
        Info: Total interconnect delay = 2.206 ns ( 40.17 % )
Info: th for register "daout[3]$latch" (data pin = "min1[3]", clock pin = "clk1") is -0.066 ns
    Info: + Longest clock path from clock "clk1" to destination register is 8.812 ns
        Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_188; Fanout = 3; CLK Node = 'clk1'
        Info: 2: + IC(1.349 ns) + CELL(0.970 ns) = 3.303 ns; Loc. = LCFF_X12_Y10_N5; Fanout = 11; REG Node = 'count[2]'
        Info: 3: + IC(0.811 ns) + CELL(0.624 ns) = 4.738 ns; Loc. = LCCOMB_X13_Y10_N0; Fanout = 1; COMB Node = 'Mux6~18'
        Info: 4: + IC(2.535 ns) + CELL(0.000 ns) = 7.273 ns; Loc. = CLKCTRL_G3; Fanout = 5; COMB Node = 'Mux6~18clkctrl'
        Info: 5: + IC(1.333 ns) + CELL(0.206 ns) = 8.812 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; REG Node = 'daout[3]$latch'
        Info: Total cell delay = 2.784 ns ( 31.59 % )
        Info: Total interconnect delay = 6.028 ns ( 68.41 % )
    Info: + Micro hold delay of destination is 0.000 ns
    Info: - Shortest pin to register delay is 8.878 ns
        Info: 1: + IC(0.000 ns) + CELL(0.984 ns) = 0.984 ns; Loc. = PIN_181; Fanout = 1; PIN Node = 'min1[3]'
        Info: 2: + IC(5.964 ns) + CELL(0.624 ns) = 7.572 ns; Loc. = LCCOMB_X13_Y10_N2; Fanout = 1; COMB Node = 'Mux5~193'
        Info: 3: + IC(0.365 ns) + CELL(0.206 ns) = 8.143 ns; Loc. = LCCOMB_X13_Y10_N8; Fanout = 1; COMB Node = 'Mux5~195'
        Info: 4: + IC(0.365 ns) + CELL(0.370 ns) = 8.878 ns; Loc. = LCCOMB_X13_Y10_N28; Fanout = 1; REG Node = 'daout[3]$latch'
        Info: Total cell delay = 2.184 ns ( 24.60 % )
        Info: Total interconnect delay = 6.694 ns ( 75.40 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 9 warnings
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Thu Nov 27 18:16:01 2008
    Info: Elapsed time: 00:00:01