deled.vhd

来自「基于fpga数字钟系统」· VHDL 代码 · 共 26 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity deled is
port (num :in std_logic_vector(3 downto 0);
     led:out std_logic_vector(6 downto 0));
end deled;
architecture fun of deled is
 begin
     led<="0000001" when num="0000" else
       "1001111" when num="0001" else
       "0010010" when num="0010" else
       "0000110"  when num="0011" else
       "1001100" when num="0100" else
       "0100100" when num="0101" else
       "0100000" when num="0110" else 
       "0001111" when num="0111" else
       "0000000" when num="1000" else
        "0000100" when num="1001" else 
        "0001000"   when num="1010" else
       "1100000"    when num="1011" else
         "0110001" when num="1100" else
        "1000010" when num="1101" else
        "0110000" when num="1110" else
        "0111000" when num="1111" ;
end fun;