fpq.tan.rpt

基于fpga数字钟系统

; N/A                                     ; 238.27 MHz ( period = 4.197 ns )                    ; count[4]  ; count[17] ; clk        ; clk      ; None                        ; None                      ; 3.936 ns                ;
; N/A                                     ; 238.44 MHz ( period = 4.194 ns )                    ; count[8]  ; count[23] ; clk        ; clk      ; None                        ; None                      ; 3.935 ns                ;
; N/A                                     ; 238.55 MHz ( period = 4.192 ns )                    ; count[18] ; count[7]  ; clk        ; clk      ; None                        ; None                      ; 3.923 ns                ;
; N/A                                     ; 238.66 MHz ( period = 4.190 ns )                    ; fmq[6]    ; fmq[19]   ; clk        ; clk      ; None                        ; None                      ; 3.927 ns                ;
; N/A                                     ; 239.01 MHz ( period = 4.184 ns )                    ; fmq[11]   ; fmq[22]   ; clk        ; clk      ; None                        ; None                      ; 3.921 ns                ;
; N/A                                     ; 239.23 MHz ( period = 4.180 ns )                    ; fmq[6]    ; fmq[14]   ; clk        ; clk      ; None                        ; None                      ; 3.916 ns                ;
; N/A                                     ; 240.15 MHz ( period = 4.164 ns )                    ; count[12] ; count[17] ; clk        ; clk      ; None                        ; None                      ; 3.900 ns                ;
; N/A                                     ; 240.44 MHz ( period = 4.159 ns )                    ; count[7]  ; count[14] ; clk        ; clk      ; None                        ; None                      ; 3.898 ns                ;
; N/A                                     ; 240.50 MHz ( period = 4.158 ns )                    ; fmq[8]    ; fmq[22]   ; clk        ; clk      ; None                        ; None                      ; 3.895 ns                ;
; N/A                                     ; 240.91 MHz ( period = 4.151 ns )                    ; count[3]  ; count[13] ; clk        ; clk      ; None                        ; None                      ; 3.890 ns                ;
; N/A                                     ; 240.91 MHz ( period = 4.151 ns )                    ; count[3]  ; count[15] ; clk        ; clk      ; None                        ; None                      ; 3.890 ns                ;
; N/A                                     ; 241.20 MHz ( period = 4.146 ns )                    ; fmq[7]    ; fmq[11]   ; clk        ; clk      ; None                        ; None                      ; 3.883 ns                ;
; N/A                                     ; 241.49 MHz ( period = 4.141 ns )                    ; fmq[17]   ; fmq[11]   ; clk        ; clk      ; None                        ; None                      ; 3.876 ns                ;
; N/A                                     ; 241.49 MHz ( period = 4.141 ns )                    ; fmq[4]    ; fmq[22]   ; clk        ; clk      ; None                        ; None                      ; 3.879 ns                ;
; N/A                                     ; 242.01 MHz ( period = 4.132 ns )                    ; fmq[9]    ; fmq[11]   ; clk        ; clk      ; None                        ; None                      ; 3.868 ns                ;
; N/A                                     ; 242.31 MHz ( period = 4.127 ns )                    ; fmq[18]   ; fmq[22]   ; clk        ; clk      ; None                        ; None                      ; 3.863 ns                ;
; N/A                                     ; 242.37 MHz ( period = 4.126 ns )                    ; fmq[5]    ; fmq[22]   ; clk        ; clk      ; None                        ; None                      ; 3.864 ns                ;
; N/A                                     ; 243.01 MHz ( period = 4.115 ns )                    ; count[19] ; count[25] ; clk        ; clk      ; None                        ; None                      ; 3.853 ns                ;
; N/A                                     ; 243.01 MHz ( period = 4.115 ns )                    ; count[1]  ; count[15] ; clk        ; clk      ; None                        ; None                      ; 3.854 ns                ;
; N/A                                     ; 243.01 MHz ( period = 4.115 ns )                    ; count[19] ; count[23] ; clk        ; clk      ; None                        ; None                      ; 3.853 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;           ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-----------+-----------+------------+----------+-----------------------------+---------------------------+-------------------------+


+---------------------------------------------------------------+
; tco                                                           ;
+-------+--------------+------------+---------+----+------------+
; Slack ; Required tco ; Actual tco ; From    ; To ; From Clock ;
+-------+--------------+------------+---------+----+------------+
; N/A   ; None         ; 8.149 ns   ; QD~reg0 ; QD ; clk        ;
; N/A   ; None         ; 7.613 ns   ; M~reg0  ; M  ; clk        ;
; N/A   ; None         ; 7.331 ns   ; QG~reg0 ; QG ; clk        ;
+-------+--------------+------------+---------+----+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Nov 28 20:49:52 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off FPQ -c FPQ --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 193.12 MHz between source register "count[22]" and destination register "count[7]" (period= 5.178 ns)
    Info: + Longest register to register delay is 4.909 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X20_Y4_N31; Fanout = 3; REG Node = 'count[22]'
        Info: 2: + IC(1.142 ns) + CELL(0.614 ns) = 1.756 ns; Loc. = LCCOMB_X19_Y4_N0; Fanout = 2; COMB Node = 'Equal0~272'
        Info: 3: + IC(0.713 ns) + CELL(0.614 ns) = 3.083 ns; Loc. = LCCOMB_X19_Y4_N20; Fanout = 12; COMB Node = 'Equal0~275'
        Info: 4: + IC(1.094 ns) + CELL(0.624 ns) = 4.801 ns; Loc. = LCCOMB_X20_Y5_N0; Fanout = 1; COMB Node = 'count~286'
        Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 4.909 ns; Loc. = LCFF_X20_Y5_N1; Fanout = 3; REG Node = 'count[7]'
        Info: Total cell delay = 1.960 ns ( 39.93 % )
        Info: Total interconnect delay = 2.949 ns ( 60.07 % )
    Info: - Smallest clock skew is -0.005 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.782 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.833 ns) + CELL(0.666 ns) = 2.782 ns; Loc. = LCFF_X20_Y5_N1; Fanout = 3; REG Node = 'count[7]'
            Info: Total cell delay = 1.806 ns ( 64.92 % )
            Info: Total interconnect delay = 0.976 ns ( 35.08 % )
        Info: - Longest clock path from clock "clk" to source register is 2.787 ns
            Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.838 ns) + CELL(0.666 ns) = 2.787 ns; Loc. = LCFF_X20_Y4_N31; Fanout = 3; REG Node = 'count[22]'
            Info: Total cell delay = 1.806 ns ( 64.80 % )
            Info: Total interconnect delay = 0.981 ns ( 35.20 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Micro setup delay of destination is -0.040 ns
Info: tco from clock "clk" to destination pin "QD" through register "QD~reg0" is 8.149 ns
    Info: + Longest clock path from clock "clk" to source register is 2.779 ns
        Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.143 ns) + CELL(0.000 ns) = 1.283 ns; Loc. = CLKCTRL_G2; Fanout = 64; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.830 ns) + CELL(0.666 ns) = 2.779 ns; Loc. = LCFF_X19_Y5_N1; Fanout = 1; REG Node = 'QD~reg0'
        Info: Total cell delay = 1.806 ns ( 64.99 % )
        Info: Total interconnect delay = 0.973 ns ( 35.01 % )
    Info: + Micro clock to output delay of source is 0.304 ns
    Info: + Longest register to pin delay is 5.066 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y5_N1; Fanout = 1; REG Node = 'QD~reg0'
        Info: 2: + IC(1.790 ns) + CELL(3.276 ns) = 5.066 ns; Loc. = PIN_180; Fanout = 0; PIN Node = 'QD'
        Info: Total cell delay = 3.276 ns ( 64.67 % )
        Info: Total interconnect delay = 1.790 ns ( 35.33 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 116 megabytes of memory during processing
    Info: Processing ended: Fri Nov 28 20:49:53 2008
    Info: Elapsed time: 00:00:01