📄 clock.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clock is
port(clk,set,s1,s2,s3:in std_logic;
second1,second2,minite1,minite2,hour1,hour2:out std_logic_vector(3 downto 0);
cout:out std_logic);
end entity;
architecture one of clock is
begin
process(clk,set,s1,s2,s3)
variable msecond1,msecond2,mminite1,mminite2,mhour11,mhour22:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if set='0' then -----启动校验
--if s1='0'
--then msecond1:=msecond1+1;
--if msecond1="1010"
-- then msecond1:="0000";
--msecond2:=msecond2+1;
-- if msecond2="0110" then msecond2:="0000";
--end if;
--end if;
--end if; --------秒校验
if s2='0' then
mminite1:=mminite1+1;
if mminite1="1010"
then mminite1:="0000";
mminite2:=mminite2+1;
if mminite2="0110"
then mminite2:="0000";
end if;
end if;
end if; ---------分校验
if s3='0' then
mhour11:=mhour11+1;
if mhour11="1010" then
mhour11:="0000";
if mhour22<"0010" then
mhour22:=mhour22+1;
end if;
elsif mhour22="0010" and mhour11="0100" then
mhour22:="0000";
mhour11:="0000";
end if;
end if;-------时校验
elsif s1='0' then
msecond1:="0000"; msecond2:="0000";
mminite1:="0000"; mminite2:="0000";
mhour11:="0000"; mhour22:="0000";
else msecond1:=msecond1+1;-----正常计时工作
if msecond1="1010"
then msecond1:="0000";
msecond2:=msecond2+1;
if msecond2="0110"
then msecond2:="0000";
cout<='1';--f
mminite1:=mminite1+1;
if mminite1="1010"
then mminite1:="0000";
mminite2:=mminite2+1;
if mminite2="0110"
then mminite2:="0000";
mhour11:=mhour11+1;
if mhour11="1010" then
mhour11:="0000";
if mhour22<"0010" then
mhour22:=mhour22+1;
end if;
elsif mhour22="0010" and mhour11="0100" then
mhour22:="0000";
mhour11:="0000";
end if;
end if;
end if;
end if;
end if;
end if;
end if;
second1<=msecond1;
second2<=msecond2;
minite1<=mminite1;
minite2<=mminite2;
hour1<=mhour11;
hour2<=mhour22;
end process;
--process(s1)
--begin
--if si='0' then
end architecture one;
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