tm.map.rpt

基于fpga数字钟系统

;     -- arithmetic mode                      ; 61    ;
;                                             ;       ;
; Total registers                             ; 91    ;
;     -- Dedicated logic registers            ; 91    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 22    ;
; Maximum fan-out node                        ; CLK   ;
; Maximum fan-out                             ; 64    ;
; Total fan-out                               ; 886   ;
; Average fan-out                             ; 2.68  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |TM                        ; 217 (1)           ; 91 (0)       ; 0           ; 0            ; 0       ; 0         ; 22   ; 0            ; |TM                 ; work         ;
;    |FPQ:inst6|             ; 122 (122)         ; 64 (64)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TM|FPQ:inst6       ; work         ;
;    |XS:inst1|              ; 3 (3)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TM|XS:inst1        ; work         ;
;    |YIMA:inst3|            ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TM|YIMA:inst3      ; work         ;
;    |clock:inst|            ; 48 (48)           ; 24 (24)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TM|clock:inst      ; work         ;
;    |deled:inst4|           ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TM|deled:inst4     ; work         ;
;    |seltime:inst2|         ; 27 (27)           ; 3 (3)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TM|seltime:inst2   ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; seltime:inst2|dp                                   ; seltime:inst2|Mux1  ; yes                    ;
; XS:inst1|y                                         ; XS:inst1|process0~0 ; yes                    ;
; seltime:inst2|daout[1]                             ; seltime:inst2|Mux1  ; yes                    ;
; seltime:inst2|daout[0]                             ; seltime:inst2|Mux1  ; yes                    ;
; seltime:inst2|daout[2]                             ; seltime:inst2|Mux1  ; yes                    ;
; seltime:inst2|daout[3]                             ; seltime:inst2|Mux1  ; yes                    ;
; Number of user-specified and inferred latches = 6  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 91    ;
; Number of registers using Synchronous Clear  ; 5     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 24    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |TM|clock:inst|msecond1[1] ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |TM|clock:inst|msecond2[2] ;
; 6:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |TM|clock:inst|mminite1[0] ;
; 7:1                ; 4 bits    ; 16 LEs        ; 4 LEs                ; 12 LEs                 ; Yes        ; |TM|clock:inst|mminite2[2] ;
; 9:1                ; 4 bits    ; 24 LEs        ; 4 LEs                ; 20 LEs                 ; Yes        ; |TM|clock:inst|mhour22[3]  ;
; 9:1                ; 4 bits    ; 24 LEs        ; 4 LEs                ; 20 LEs                 ; Yes        ; |TM|clock:inst|mhour11[2]  ;
; 6:1                ; 4 bits    ; 16 LEs        ; 16 LEs               ; 0 LEs                  ; No         ; |TM|seltime:inst2|Mux5     ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Nov 28 21:19:42 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off TM -c TM
Info: Found 1 design units, including 1 entities, in source file TM.bdf
    Info: Found entity 1: TM
Info: Found 2 design units, including 1 entities, in source file deled.vhd
    Info: Found design unit 1: deled-fun
    Info: Found entity 1: deled
Info: Found 2 design units, including 1 entities, in source file XS.vhd
    Info: Found design unit 1: XS-m
    Info: Found entity 1: XS
Info: Elaborating entity "TM" for the top level hierarchy
Warning: Using design file seltime.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: seltime-fun
    Info: Found entity 1: seltime
Info: Elaborating entity "seltime" for hierarchy "seltime:inst2"
Warning (10492): VHDL Process Statement warning at seltime.vhd(26): signal "count" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(27): signal "sec0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(28): signal "sec1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(29): signal "min0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(30): signal "min1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(31): signal "hh0" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at seltime.vhd(32): signal "hh1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at seltime.vhd(17): inferring latch(es) for signal or variable "daout", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at seltime.vhd(17): inferring latch(es) for signal or variable "dp", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "dp" at seltime.vhd(17)
Info (10041): Inferred latch for "daout[0]" at seltime.vhd(17)
Info (10041): Inferred latch for "daout[1]" at seltime.vhd(17)
Info (10041): Inferred latch for "daout[2]" at seltime.vhd(17)
Info (10041): Inferred latch for "daout[3]" at seltime.vhd(17)
Warning: Using design file FPQ.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: FPQ-cc
    Info: Found entity 1: FPQ
Info: Elaborating entity "FPQ" for hierarchy "FPQ:inst6"
Warning: Using design file clock.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: clock-one
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for hierarchy "clock:inst"
Info: Elaborating entity "XS" for hierarchy "XS:inst1"
Warning (10492): VHDL Process Statement warning at XS.vhd(25): signal "clk" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at XS.vhd(11): inferring latch(es) for signal or variable "y", which holds its previous value in one or more paths through the process
Info (10041): Inferred latch for "y" at XS.vhd(15)
Info: Elaborating entity "deled" for hierarchy "deled:inst4"
Info (10041): Inferred latch for "led[0]" at deled.vhd(10)
Info (10041): Inferred latch for "led[1]" at deled.vhd(10)
Info (10041): Inferred latch for "led[2]" at deled.vhd(10)
Info (10041): Inferred latch for "led[3]" at deled.vhd(10)
Info (10041): Inferred latch for "led[4]" at deled.vhd(10)
Info (10041): Inferred latch for "led[5]" at deled.vhd(10)
Info (10041): Inferred latch for "led[6]" at deled.vhd(10)
Warning: Using design file YIMA.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: YIMA-baby
    Info: Found entity 1: YIMA
Info: Elaborating entity "YIMA" for hierarchy "YIMA:inst3"
Warning: Latch seltime:inst2|dp has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal seltime:inst2|count[2]
Warning: Latch seltime:inst2|daout[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal seltime:inst2|count[2]
Warning: Latch seltime:inst2|daout[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal seltime:inst2|count[2]
Warning: Latch seltime:inst2|daout[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal seltime:inst2|count[2]
Warning: Latch seltime:inst2|daout[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal seltime:inst2|count[2]
Info: Implemented 239 device resources after synthesis - the final resource count might be different
    Info: Implemented 5 input pins
    Info: Implemented 17 output pins
    Info: Implemented 217 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 25 warnings
    Info: Allocated 165 megabytes of memory during processing
    Info: Processing ended: Fri Nov 28 21:19:46 2008
    Info: Elapsed time: 00:00:04