seltime.vhd

来自「基于fpga数字钟系统」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity seltime is
port (sec0,sec1,min0,min1:in std_logic_vector(3 downto 0);
      hh0,hh1:in std_logic_vector(3 downto 0);
      clk1:in std_logic;
      daout:out std_logic_vector(3 downto 0);
      dp:out std_logic;
      sel:out std_logic_vector(2 downto 0));
end seltime;
architecture fun of seltime is
signal count: std_logic_vector(2 downto 0);
begin
sel<=count;
process(clk1)
  begin
      if (clk1'event and clk1='1') then
           if count>="101" then
              count<="000";
            else
              count<=count+1;
           end if;
        end if;
case count is
 when "000" => daout<=sec0;dp<='1';
 when "001" => daout<=sec1;dp<='1';
 when "010" => daout<=min0;dp<='0';
 when "011" => daout<=min1;dp<='1';
 when "100" => daout<=hh0; dp<='0';
 when "101" =>daout<=hh1;dp<='1';
 when others => daout<=null;
end case;
end process;
end fun;