fpq.vhd

基于fpga数字钟系统

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned;
entity FPQ IS
port(clk:in std_logic;
     QG,QD,M:out std_logic);
END FPQ;
architecture cc of FPQ IS
SIGNAL count:INTEGER RANGE 0 TO 49999999;
SIGNAL MOUNT:INTEGER RANGE 0 TO 3000;
signal fmq:integer range 0 to 5000000;
begin
process(clk)
BEGIN
if clk'event and clk='1' then
         
        count<=count+1;
           if count=49999999 then
             count<=0;
           end if;
    if count<= 24999999 then
       QD<='0';
    elsif count > 24999999 then
       QD<='1';
  
    end if;
end if;
END PROCESS;
process(clk)
begin
if clk'event and clk='1' then
           MOUNT<=MOUNT+1;
           if MOUNT=3000 then
             MOUNT<=0;
           end if;
    if MOUNT<= 1500 then
       QG<='0';
    elsif MOUNT > 1500 then
       QG<='1';
     END IF;
END IF;
end process;
process(clk)
begin
if clk'event and clk='1' then
           fmq<=fmq+1;
           if fmq=500000 then
            fmq<=0;
           end if;
    if fmq<= 250000 then
       M<='0';
    elsif fmq > 250000 then
       M<='1';
     END IF;
END IF;
end process;
end cc;