📄 xs.tan.rpt
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Classic Timing Analyzer report for XS
Fri Nov 28 21:18:07 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.179 ns ; clk ; y ; -- ; a1[0] ; 0 ;
; Worst-case tco ; N/A ; None ; 7.948 ns ; y ; sc ; a1[2] ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -4.069 ns ; clk ; y ; -- ; a1[2] ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+------+----+------------+----------+--------------+
+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5Q208C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; a1[3] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; a1[1] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; a1[0] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; a0[3] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; a1[2] ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+----------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+----+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+----+----------+
; N/A ; None ; 6.179 ns ; clk ; y ; a1[0] ;
; N/A ; None ; 5.953 ns ; clk ; y ; a0[3] ;
; N/A ; None ; 5.873 ns ; clk ; y ; a1[3] ;
; N/A ; None ; 5.443 ns ; clk ; y ; a1[1] ;
; N/A ; None ; 5.272 ns ; clk ; y ; a1[2] ;
+-------+--------------+------------+------+----+----------+
+------------------------------------------------------------+
; tco ;
+-------+--------------+------------+------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+------+----+------------+
; N/A ; None ; 7.948 ns ; y ; sc ; a1[2] ;
; N/A ; None ; 7.777 ns ; y ; sc ; a1[1] ;
; N/A ; None ; 7.347 ns ; y ; sc ; a1[3] ;
; N/A ; None ; 7.267 ns ; y ; sc ; a0[3] ;
; N/A ; None ; 7.041 ns ; y ; sc ; a1[0] ;
+-------+--------------+------------+------+----+------------+
+----------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+----+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+----+----------+
; N/A ; None ; -4.069 ns ; clk ; y ; a1[2] ;
; N/A ; None ; -4.240 ns ; clk ; y ; a1[1] ;
; N/A ; None ; -4.670 ns ; clk ; y ; a1[3] ;
; N/A ; None ; -4.750 ns ; clk ; y ; a0[3] ;
; N/A ; None ; -4.976 ns ; clk ; y ; a1[0] ;
+---------------+-------------+-----------+------+----+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
Info: Processing started: Fri Nov 28 21:18:07 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off XS -c XS --timing_analysis_only
Warning: Timing Analysis is analyzing one or more combinational loops as latches
Warning: Node "y" is a latch
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "a1[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Assuming node "a1[1]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Assuming node "a1[0]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Assuming node "a0[3]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Info: Assuming node "a1[2]" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin.
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected gated clock "process0~0" as buffer
Info: Detected gated clock "process0~30" as buffer
Info: tsu for register "y" (data pin = "clk", clock pin = "a1[0]") is 6.179 ns
Info: + Longest pin to register delay is 7.867 ns
Info: 1: + IC(0.000 ns) + CELL(1.014 ns) = 1.014 ns; Loc. = PIN_207; Fanout = 1; PIN Node = 'clk'
Info: 2: + IC(6.203 ns) + CELL(0.650 ns) = 7.867 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'
Info: Total cell delay = 1.664 ns ( 21.15 % )
Info: Total interconnect delay = 6.203 ns ( 78.85 % )
Info: + Micro setup delay of destination is 1.203 ns
Info: - Shortest clock path from clock "a1[0]" to destination register is 2.891 ns
Info: 1: + IC(0.000 ns) + CELL(0.985 ns) = 0.985 ns; Loc. = PIN_30; Fanout = 1; CLK Node = 'a1[0]'
Info: 2: + IC(0.968 ns) + CELL(0.370 ns) = 2.323 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 1; COMB Node = 'process0~0'
Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 2.891 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'
Info: Total cell delay = 1.561 ns ( 54.00 % )
Info: Total interconnect delay = 1.330 ns ( 46.00 % )
Info: tco from clock "a1[2]" to destination pin "sc" through register "y" is 7.948 ns
Info: + Longest clock path from clock "a1[2]" to source register is 3.798 ns
Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'a1[2]'
Info: 2: + IC(1.621 ns) + CELL(0.614 ns) = 3.230 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 1; COMB Node = 'process0~0'
Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 3.798 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'
Info: Total cell delay = 1.815 ns ( 47.79 % )
Info: Total interconnect delay = 1.983 ns ( 52.21 % )
Info: + Micro clock to output delay of source is 0.000 ns
Info: + Longest register to pin delay is 4.150 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'
Info: 2: + IC(1.054 ns) + CELL(3.096 ns) = 4.150 ns; Loc. = PIN_34; Fanout = 0; PIN Node = 'sc'
Info: Total cell delay = 3.096 ns ( 74.60 % )
Info: Total interconnect delay = 1.054 ns ( 25.40 % )
Info: th for register "y" (data pin = "clk", clock pin = "a1[2]") is -4.069 ns
Info: + Longest clock path from clock "a1[2]" to destination register is 3.798 ns
Info: 1: + IC(0.000 ns) + CELL(0.995 ns) = 0.995 ns; Loc. = PIN_12; Fanout = 1; CLK Node = 'a1[2]'
Info: 2: + IC(1.621 ns) + CELL(0.614 ns) = 3.230 ns; Loc. = LCCOMB_X1_Y5_N0; Fanout = 1; COMB Node = 'process0~0'
Info: 3: + IC(0.362 ns) + CELL(0.206 ns) = 3.798 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'
Info: Total cell delay = 1.815 ns ( 47.79 % )
Info: Total interconnect delay = 1.983 ns ( 52.21 % )
Info: + Micro hold delay of destination is 0.000 ns
Info: - Shortest pin to register delay is 7.867 ns
Info: 1: + IC(0.000 ns) + CELL(1.014 ns) = 1.014 ns; Loc. = PIN_207; Fanout = 1; PIN Node = 'clk'
Info: 2: + IC(6.203 ns) + CELL(0.650 ns) = 7.867 ns; Loc. = LCCOMB_X1_Y5_N22; Fanout = 1; REG Node = 'y'
Info: Total cell delay = 1.664 ns ( 21.15 % )
Info: Total interconnect delay = 6.203 ns ( 78.85 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings
Info: Allocated 115 megabytes of memory during processing
Info: Processing ended: Fri Nov 28 21:18:08 2008
Info: Elapsed time: 00:00:01
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