yima.vhd

来自「基于fpga数字钟系统」· VHDL 代码 · 共 21 行

library ieee;
use ieee.std_logic_1164.all;
entity YIMA is
port(a:in std_logic_vector(2 downto 0);
     y:out std_Logic_vector(7 downto 0));
end YIMA;
architecture baby of YIMA is
signal sa :std_logic_vector(2 downto 0);
begin
sa<=a;
with sa select
y<="11111110" when "000",
"11111101" when "001",
"11111011" when "010",
"11110111" when "011",
"11101111" when "100",
"11011111" when "101",
"10111111" when "110",
"01111111" when "111",
"11111111" when OTHERS;
end baby;