prev_cmp_project3.qmsg

用VHDL语言实现一个10秒倒计时电路

{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "129 " "Info: Allocated 129 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 24 00:16:07 2008 " "Info: Processing ended: Wed Dec 24 00:16:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 24 00:16:08 2008 " "Info: Processing started: Wed Dec 24 00:16:08 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off project3 -c project3 " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off project3 -c project3" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 8 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cou1 " "Info: Detected ripple clock \"cou1\" as buffer" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 19 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "cou1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk2 " "Info: Detected ripple clock \"clk2\" as buffer" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk1 " "Info: Detected ripple clock \"clk1\" as buffer" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } } { "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register ctrl_c\[0\] register alarm~reg0 70.58 MHz 14.168 ns Internal " "Info: Clock \"clk\" has Internal fmax of 70.58 MHz between source register \"ctrl_c\[0\]\" and destination register \"alarm~reg0\" (period= 14.168 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.478 ns + Longest register register " "Info: + Longest register to register delay is 2.478 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ctrl_c\[0\] 1 REG LC_X8_Y4_N0 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y4_N0; Fanout = 8; REG Node = 'ctrl_c\[0\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { ctrl_c[0] } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.071 ns) + CELL(0.511 ns) 1.582 ns Equal3~62 2 COMB LC_X8_Y4_N6 2 " "Info: 2: + IC(1.071 ns) + CELL(0.511 ns) = 1.582 ns; Loc. = LC_X8_Y4_N6; Fanout = 2; COMB Node = 'Equal3~62'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.582 ns" { ctrl_c[0] Equal3~62 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 70 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.591 ns) 2.478 ns alarm~reg0 3 REG LC_X8_Y4_N7 3 " "Info: 3: + IC(0.305 ns) + CELL(0.591 ns) = 2.478 ns; Loc. = LC_X8_Y4_N7; Fanout = 3; REG Node = 'alarm~reg0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.896 ns" { Equal3~62 alarm~reg0 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.102 ns ( 44.47 % ) " "Info: Total cell delay = 1.102 ns ( 44.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.376 ns ( 55.53 % ) " "Info: Total interconnect delay = 1.376 ns ( 55.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.478 ns" { ctrl_c[0] Equal3~62 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "2.478 ns" { ctrl_c[0] {} Equal3~62 {} alarm~reg0 {} } { 0.000ns 1.071ns 0.305ns } { 0.000ns 0.511ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.897 ns - Smallest " "Info: - Smallest clock skew is -3.897 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 9.054 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 9.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk2 2 REG LC_X11_Y4_N1 6 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X11_Y4_N1; Fanout = 6; REG Node = 'clk2'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk2 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.941 ns) + CELL(0.918 ns) 9.054 ns alarm~reg0 3 REG LC_X8_Y4_N7 3 " "Info: 3: + IC(3.941 ns) + CELL(0.918 ns) = 9.054 ns; Loc. = LC_X8_Y4_N7; Fanout = 3; REG Node = 'alarm~reg0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.859 ns" { clk2 alarm~reg0 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 37.28 % ) " "Info: Total cell delay = 3.375 ns ( 37.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.679 ns ( 62.72 % ) " "Info: Total interconnect delay = 5.679 ns ( 62.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.054 ns" { clk clk2 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "9.054 ns" { clk {} clk~combout {} clk2 {} alarm~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.941ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.951 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.951 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk1 2 REG LC_X12_Y3_N3 22 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N3; Fanout = 22; REG Node = 'clk1'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk1 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(1.294 ns) 8.517 ns cou1 3 REG LC_X13_Y3_N2 3 " "Info: 3: + IC(3.028 ns) + CELL(1.294 ns) = 8.517 ns; Loc. = LC_X13_Y3_N2; Fanout = 3; REG Node = 'cou1'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.322 ns" { clk1 cou1 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.516 ns) + CELL(0.918 ns) 12.951 ns ctrl_c\[0\] 4 REG LC_X8_Y4_N0 8 " "Info: 4: + IC(3.516 ns) + CELL(0.918 ns) = 12.951 ns; Loc. = LC_X8_Y4_N0; Fanout = 8; REG Node = 'ctrl_c\[0\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.434 ns" { cou1 ctrl_c[0] } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 36.05 % ) " "Info: Total cell delay = 4.669 ns ( 36.05 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.282 ns ( 63.95 % ) " "Info: Total interconnect delay = 8.282 ns ( 63.95 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "12.951 ns" { clk clk1 cou1 ctrl_c[0] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "12.951 ns" { clk {} clk~combout {} clk1 {} cou1 {} ctrl_c[0] {} } { 0.000ns 0.000ns 1.738ns 3.028ns 3.516ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.054 ns" { clk clk2 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "9.054 ns" { clk {} clk~combout {} clk2 {} alarm~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.941ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "12.951 ns" { clk clk1 cou1 ctrl_c[0] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "12.951 ns" { clk {} clk~combout {} clk1 {} cou1 {} ctrl_c[0] {} } { 0.000ns 0.000ns 1.738ns 3.028ns 3.516ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 -1 0 } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 75 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.478 ns" { ctrl_c[0] Equal3~62 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "2.478 ns" { ctrl_c[0] {} Equal3~62 {} alarm~reg0 {} } { 0.000ns 1.071ns 0.305ns } { 0.000ns 0.511ns 0.591ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "9.054 ns" { clk clk2 alarm~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "9.054 ns" { clk {} clk~combout {} clk2 {} alarm~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.941ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "12.951 ns" { clk clk1 cou1 ctrl_c[0] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "12.951 ns" { clk {} clk~combout {} clk1 {} cou1 {} ctrl_c[0] {} } { 0.000ns 0.000ns 1.738ns 3.028ns 3.516ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk col\[7\] col\[7\]~reg0 13.530 ns register " "Info: tco from clock \"clk\" to destination pin \"col\[7\]\" through register \"col\[7\]~reg0\" is 13.530 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.141 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.141 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_18 39 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_18; Fanout = 39; CLK Node = 'clk'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.738 ns) + CELL(1.294 ns) 4.195 ns clk1 2 REG LC_X12_Y3_N3 22 " "Info: 2: + IC(1.738 ns) + CELL(1.294 ns) = 4.195 ns; Loc. = LC_X12_Y3_N3; Fanout = 22; REG Node = 'clk1'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.032 ns" { clk clk1 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.028 ns) + CELL(0.918 ns) 8.141 ns col\[7\]~reg0 3 REG LC_X9_Y7_N2 1 " "Info: 3: + IC(3.028 ns) + CELL(0.918 ns) = 8.141 ns; Loc. = LC_X9_Y7_N2; Fanout = 1; REG Node = 'col\[7\]~reg0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.946 ns" { clk1 col[7]~reg0 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 197 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 41.46 % ) " "Info: Total cell delay = 3.375 ns ( 41.46 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.766 ns ( 58.54 % ) " "Info: Total interconnect delay = 4.766 ns ( 58.54 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { clk clk1 col[7]~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { clk {} clk~combout {} clk1 {} col[7]~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 197 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.013 ns + Longest register pin " "Info: + Longest register to pin delay is 5.013 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns col\[7\]~reg0 1 REG LC_X9_Y7_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y7_N2; Fanout = 1; REG Node = 'col\[7\]~reg0'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { col[7]~reg0 } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 197 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.691 ns) + CELL(2.322 ns) 5.013 ns col\[7\] 2 PIN PIN_138 0 " "Info: 2: + IC(2.691 ns) + CELL(2.322 ns) = 5.013 ns; Loc. = PIN_138; Fanout = 0; PIN Node = 'col\[7\]'" {  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.013 ns" { col[7]~reg0 col[7] } "NODE_NAME" } } { "project3.vhd" "" { Text "E:/project3/project3.vhd" 197 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.32 % ) " "Info: Total cell delay = 2.322 ns ( 46.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.691 ns ( 53.68 % ) " "Info: Total interconnect delay = 2.691 ns ( 53.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.013 ns" { col[7]~reg0 col[7] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "5.013 ns" { col[7]~reg0 {} col[7] {} } { 0.000ns 2.691ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.141 ns" { clk clk1 col[7]~reg0 } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "8.141 ns" { clk {} clk~combout {} clk1 {} col[7]~reg0 {} } { 0.000ns 0.000ns 1.738ns 3.028ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "5.013 ns" { col[7]~reg0 col[7] } "NODE_NAME" } } { "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartusii/quartus/bin/Technology_Viewer.qrui" "5