prev_cmp_project3.qmsg

用VHDL语言实现一个10秒倒计时电路

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Dec 24 00:15:32 2008 " "Info: Processing started: Wed Dec 24 00:15:32 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off project3 -c project3 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off project3 -c project3" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "project3.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file project3.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 project3-behave " "Info: Found design unit 1: project3-behave" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 12 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 project3 " "Info: Found entity 1: project3" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "project3 " "Info: Elaborating entity \"project3\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "cou1 project3.vhd(57) " "Warning (10492): VHDL Process Statement warning at project3.vhd(57): signal \"cou1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 57 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count project3.vhd(71) " "Warning (10492): VHDL Process Statement warning at project3.vhd(71): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 71 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "count project3.vhd(88) " "Warning (10492): VHDL Process Statement warning at project3.vhd(88): signal \"count\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 88 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "row\[7\]~reg0 data_in GND " "Warning (14130): Reduced register \"row\[7\]~reg0\" with stuck data_in port to stuck value GND" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 197 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "row\[2\]~reg0 row\[3\]~reg0 " "Info: Duplicate register \"row\[2\]~reg0\" merged to single register \"row\[3\]~reg0\"" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 197 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "count2\[0\] count1\[0\] " "Info: Duplicate register \"count2\[0\]\" merged to single register \"count1\[0\]\"" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "count2\[1\] count1\[1\] " "Info: Duplicate register \"count2\[1\]\" merged to single register \"count1\[1\]\"" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "count2\[2\] count1\[2\] " "Info: Duplicate register \"count2\[2\]\" merged to single register \"count1\[2\]\"" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "count2\[3\] count1\[3\] " "Info: Duplicate register \"count2\[3\]\" merged to single register \"count1\[3\]\"" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 26 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0 "" 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "row\[7\] GND " "Warning (13410): Pin \"row\[7\]\" stuck at GND" {  } { { "project3.vhd" "" { Text "E:/project3/project3.vhd" 197 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "177 " "Info: Implemented 177 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "158 " "Info: Implemented 158 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "163 " "Info: Allocated 163 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Dec 24 00:15:39 2008 " "Info: Processing ended: Wed Dec 24 00:15:39 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}