project3.map.summary

用VHDL语言实现一个10秒倒计时电路

Analysis & Synthesis Status : Successful - Wed Dec 24 00:19:47 2008
Quartus II Version : 7.2 Build 151 09/26/2007 SJ Full Version
Revision Name : project3
Top-level Entity Name : project3
Family : MAX II
Total logic elements : 158
Total pins : 19
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0