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📄 project3.fit.rpt

📁 用VHDL语言实现一个10秒倒计时电路
💻 RPT
📖 第 1 页 / 共 5 页
字号:
; 5                                               ; 1                            ;
; 6                                               ; 1                            ;
; 7                                               ; 4                            ;
; 8                                               ; 4                            ;
; 9                                               ; 2                            ;
; 10                                              ; 2                            ;
+-------------------------------------------------+------------------------------+


+----------------------------------------------------------------------------+
; LAB Distinct Inputs                                                        ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs  (Average = 6.38) ; Number of LABs  (Total = 24) ;
+---------------------------------------------+------------------------------+
; 0                                           ; 0                            ;
; 1                                           ; 0                            ;
; 2                                           ; 9                            ;
; 3                                           ; 0                            ;
; 4                                           ; 0                            ;
; 5                                           ; 0                            ;
; 6                                           ; 2                            ;
; 7                                           ; 3                            ;
; 8                                           ; 3                            ;
; 9                                           ; 2                            ;
; 10                                          ; 2                            ;
; 11                                          ; 2                            ;
; 12                                          ; 0                            ;
; 13                                          ; 0                            ;
; 14                                          ; 0                            ;
; 15                                          ; 0                            ;
; 16                                          ; 0                            ;
; 17                                          ; 0                            ;
; 18                                          ; 1                            ;
+---------------------------------------------+------------------------------+


+-------------------------------------------------------------------------+
; Fitter Device Options                                                   ;
+----------------------------------------------+--------------------------+
; Option                                       ; Setting                  ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                      ;
; Enable device-wide reset (DEV_CLRn)          ; Off                      ;
; Enable device-wide output enable (DEV_OE)    ; Off                      ;
; Enable INIT_DONE output                      ; Off                      ;
; Configuration scheme                         ; Passive Serial           ;
; Reserve all unused pins                      ; As output driving ground ;
; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-----------------------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                                         ;
+--------------------------------------------------------------------------------+--------------+
; Name                                                                           ; Value        ;
+--------------------------------------------------------------------------------+--------------+
; Auto Fit Point 1 - Fit Attempt 1                                               ; ff           ;
; Mid Wire Use - Fit Attempt 1                                                   ; 7            ;
; Mid Slack - Fit Attempt 1                                                      ; -13115       ;
; Internal Atom Count - Fit Attempt 1                                            ; 146          ;
; LE/ALM Count - Fit Attempt 1                                                   ; 146          ;
; LAB Count - Fit Attempt 1                                                      ; 24           ;
; Outputs per Lab - Fit Attempt 1                                                ; 4.958        ;
; Inputs per LAB - Fit Attempt 1                                                 ; 5.292        ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 1.083        ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:21;1:3     ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:24         ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:20;1:4     ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:20;1:4     ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:20;1:4     ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:20;1:4     ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:23;1:1     ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:24         ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:21;1:3     ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:1;1:20;2:3 ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:1;1:20;2:3 ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:21;1:3     ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:1;1:20;2:3 ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:18;1:6     ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 0:9;1:15     ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:19;1:5     ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:24         ;
; LEs in Chains - Fit Attempt 1                                                  ; 40           ;
; LEs in Long Chains - Fit Attempt 1                                             ; 40           ;
; LABs with Chains - Fit Attempt 1                                               ; 5            ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0            ;
; Time - Fit Attempt 1                                                           ; 0            ;
+--------------------------------------------------------------------------------+--------------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Auto Fit Point 2 - Fit Attempt 1    ; ff     ;
; Early Wire Use - Fit Attempt 1      ; 2      ;
; Early Slack - Fit Attempt 1         ; -16411 ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Auto Fit Point 4 - Fit Attempt 1    ; ff     ;
; Mid Wire Use - Fit Attempt 1        ; 3      ;
; Mid Slack - Fit Attempt 1           ; -13513 ;
; Auto Fit Point 5 - Fit Attempt 1    ; ff     ;
; Late Wire Use - Fit Attempt 1       ; 4      ;
; Late Slack - Fit Attempt 1          ; -13513 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Auto Fit Point 6 - Fit Attempt 1    ; ff     ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.063  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -13073 ;
; Early Wire Use - Fit Attempt 1      ; 3      ;
; Peak Regional Wire - Fit Attempt 1  ; 3      ;
; Mid Slack - Fit Attempt 1           ; -13136 ;
; Late Slack - Fit Attempt 1          ; -13136 ;
; Late Wire Use - Fit Attempt 1       ; 4      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.047  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Wed Dec

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