ri.vhdl

来自「source and benchmark test for the regist」· VHDL 代码 · 共 36 行

library ieee;
use ieee.std_logic_1164.all;
entity instr_reg is
port(
CLK :    in std_logic;
ce :     in std_logic;
rst :    in std_logic;
instr :in std_logic_vector(15 downto 0);
cond :   out std_logic_vector(3 downto 0);
op :     out std_logic_vector(3 downto 0);
updt:    out std_logic;
imm:     out std_logic;
val:     out std_logic_vector(5 downto 0)
);end instr_reg;

architecture BEHAVE of instr_reg is
signal tmp : std_logic_vector(15 downto 0);
begin
process(CLK)
   begin
if rising_edge(CLK)then
   if rst = '1' then 
      tmp <="ZZZZZZZZZZZZZZZZ";
   else
   if (ce='1') then      --reset=0
      tmp<=instr;
    end if;-- end de ce
   end if;--ende de rst
   end if;--end de CLK
end process;
cond <= tmp(15 downto 12);
op <= tmp(11 downto 8);
updt <= tmp(7);
imm <= tmp(8);
val <= tmp(5 downto 0);
end BEHAVE;