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# Reading C:/Modeltech_6.2b/tcl/vsim/pref.tcl
# // ModelSim SE 6.2b Jul 31 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# OpenFile {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
vsim -gui work.instr_reg_test
# vsim -gui work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
add wave sim:/instr_reg_test/*
run -all
run -all
run
run
run
run
run
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
quit -sim
vsim -gui work.instr_reg_test
# vsim -gui work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
add wave sim:/instr_reg_test/*
run
run
run
quit -sim
vsim work.instr_reg
# vsim work.instr_reg
# ** Note: (vsim-3812) Design is being optimized...
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading work.instr_reg(behave)
quit -sim
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
vsim work.instr_reg_test
# vsim work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
add wave sim:/instr_reg_test/*
run
run
run
quit -sim
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
# ** Error: C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl(33): (vcom-1136) Unknown identifier "datatemp".
# ** Error: C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl(34): (vcom-1136) Unknown identifier "datatemp".
# ** Error: C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl(35): (vcom-1136) Unknown identifier "datatemp".
# ** Error: C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl(36): (vcom-1136) Unknown identifier "datatemp".
# ** Error: C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl(37): (vcom-1136) Unknown identifier "datatemp".
# ** Error: C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl(38): VHDL Compiler exiting
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
vsim work.instr_reg_test
# vsim work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
add wave sim:/instr_reg_test/*
run -all
run
run
run
quit -sim
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vsim work.instr_reg_test
# vsim work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
add wave sim:/instr_reg_test/*
run
quit -sim
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
vsim work.instr_reg_test
# vsim work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
add wave sim:/instr_reg_test/*
run
run
quit -sim
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
vsim work.instr_reg_test
# vsim work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
add wave sim:/instr_reg_test/*
run
run
run
quit -sim
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
vsim work.instr_reg_test
# vsim work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
add wave sim:/instr_reg_test/*
run -all
run
run
quit -sim
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Compiling entity instr_reg
# -- Compiling architecture behave of instr_reg
vcom -reportprogress 300 -work work {C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl}
# Model Technology ModelSim SE vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package std_logic_arith
# -- Compiling entity instr_reg_test
# -- Compiling architecture arch of instr_reg_test
vsim work.instr_reg_test
# vsim work.instr_reg_test
# Loading C:\Modeltech_6.2b\win32/../std.standard
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_1164(body)
# Loading C:\Modeltech_6.2b\win32/../ieee.std_logic_arith(body)
# Loading work.instr_reg_test(arch)
# ** Warning: (vsim-3473) Component instance "instr_reg_0 : instr_reg" is not bound.
# Time: 0 ns Iteration: 0 Region: /instr_reg_test File: C:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
add wave sim:/instr_reg_test/*
run
run
run
quit -sim
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