bancregistre.vhdl

来自「source and benchmark test for the regist」· VHDL 代码 · 共 22 行

LIBRARY ieee;
library	ieee;
use ieee.std_logic_1164.all;  
use ieee.std_logic_arith.all;			   
use ieee.std_logic_unsigned.all;   

entity reg_file is
port(	clk:	   in std_logic;                        --Horloge
      rst:	   in std_logic;                        --reset
      
      acc_out:out std_logic_vector(15 downto 0);--sortie de l'accumulateur
      acc_ce:	in std_logic;                     --enable accumulateur
      
      pc_out:	 out std_logic_vector(15 downto 0); --sortie de pc
		rpc_ce:	in std_logic;
		pc_ce:	 in std_logic;
		                     
		rx_num:	in std_logic_vector(5 downto 0);--Bus de 6 bits pour selectionner le registre		
		rx_ce:	 in std_logic;                      --enable registre x
		rx_out: out std_logic_vector(15 downto 0);--sortie de registre rx
		
		din:    in std_logic_vector(15 downto 0)     --entr