work__info

source and benchmark test for the registery parts of a RISC processor

m255
13
cModel Technology
dC:\Documents and Settings\alibb\Bureau\travailRawefi
T_opt
V[@VcC:DlaNJC?T4PV?;6b3
04 14 4 work instr_reg_test arch 0
o-quiet -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
T_opt1
VfE8D2THGCjAG`l?iGAk4f1
04 9 6 work instr_reg behave 0
o-quiet -auto_acc_if_foreign -work work
tExplicit 1
OE;O;6.2b;35
Einstr_reg
w1241349437
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
32
dC:\Documents and Settings\alibb\Bureau\travailRawefi
FC:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl
l0
L3
VhicBF__;iCU`anEEg7eP>0
OE;C;6.2b;35
o-work work
tExplicit 1
Abehave
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work instr_reg hicBF__;iCU`anEEg7eP>0
32
M1 ieee std_logic_1164
l19
L17
VbBgb>jD2mYU>PMjS=7R_M2
OE;C;6.2b;35
o-work work
tExplicit 1
Einstr_reg_test
w1241347526
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dC:\Documents and Settings\alibb\Bureau\travailRawefi
FC:/Documents and Settings/alibb/Bureau/travailRawefi/TestBenchRi.vhdl
l0
L5
V035b`G^BNYz<FcQZ10^5B2
OE;C;6.2b;35
32
o-work work
tExplicit 1
Aarch
DP ieee std_logic_arith GJbAT?7@hRQU9IQ702DT]2
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work instr_reg_test 035b`G^BNYz<FcQZ10^5B2
l36
L8
VP7Z=943e7E_<RX3z7`Q1B1
OE;C;6.2b;35
32
M2 ieee std_logic_1164
M1 ieee std_logic_arith
o-work work
tExplicit 1
Eri
w1241348797
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
dC:\Documents and Settings\alibb\Bureau\travailRawefi
FC:/Documents and Settings/alibb/Bureau/travailRawefi/RI.vhdl
l0
L3
VzzG_kn8RF3^c02I[0=QRa1
OE;C;6.2b;35
32
o-work work
tExplicit 1
Abehave
DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2
DE work ri zzG_kn8RF3^c02I[0=QRa1
l19
L17
V<C0HFoEXK[>Ng4aUX`LEJ1
OE;C;6.2b;35
32
M1 ieee std_logic_1164
o-work work
tExplicit 1