alert.rpt

有关数字钟的

-- Node name is ':155' 
-- Equation name is '_LC1_A3', type is buried 
!_LC1_A3 = _LC1_A3~NOT;
_LC1_A3~NOT = LCELL( _EQ013);
  _EQ013 = !minute6
         #  minute5
         # !_LC3_A3
         #  minute7;

-- Node name is '~397~1' 
-- Equation name is '~397~1', location is LC4_B4, type is buried.
-- synthesized logic cell 
_LC4_B4  = LCELL( _EQ014);
  _EQ014 = !_LC1_C7 & !second1 & !second2 &  second3;

-- Node name is ':397' 
-- Equation name is '_LC7_B4', type is buried 
_LC7_B4  = LCELL( _EQ015);
  _EQ015 =  _LC4_B4 &  second0;

-- Node name is ':417' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = LCELL( _EQ016);
  _EQ016 =  _LC4_B4 & !second0;

-- Node name is '~477~1' 
-- Equation name is '~477~1', location is LC1_C7, type is buried.
-- synthesized logic cell 
!_LC1_C7 = _LC1_C7~NOT;
_LC1_C7~NOT = LCELL( _EQ017);
  _EQ017 =  second4 & !second5 &  second6 & !second7;

-- Node name is ':497' 
-- Equation name is '_LC4_C7', type is buried 
_LC4_C7  = LCELL( _EQ018);
  _EQ018 =  _LC2_C7 & !second1 &  second2;

-- Node name is '~517~1' 
-- Equation name is '~517~1', location is LC2_B4, type is buried.
-- synthesized logic cell 
!_LC2_B4 = _LC2_B4~NOT;
_LC2_B4~NOT = LCELL( _EQ019);
  _EQ019 = !_LC1_C7 &  second0 &  second1 & !second3;

-- Node name is '~537~1' 
-- Equation name is '~537~1', location is LC2_C7, type is buried.
-- synthesized logic cell 
_LC2_C7  = LCELL( _EQ020);
  _EQ020 = !_LC1_C7 & !second0 & !second3;

-- Node name is '~537~2' 
-- Equation name is '~537~2', location is LC1_B4, type is buried.
-- synthesized logic cell 
_LC1_B4  = LCELL( _EQ021);
  _EQ021 = !_LC1_C7 & !second0 &  second1 & !second3;

-- Node name is '~557~1' 
-- Equation name is '~557~1', location is LC6_B4, type is buried.
-- synthesized logic cell 
!_LC6_B4 = _LC6_B4~NOT;
_LC6_B4~NOT = LCELL( _EQ022);
  _EQ022 = !_LC1_C7 &  second0 & !second1 & !second3;

-- Node name is ':557' 
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = LCELL( _EQ023);
  _EQ023 = !_LC6_B4 & !second2;

-- Node name is ':602' 
-- Equation name is '_LC5_B1', type is buried 
_LC5_B1  = LCELL( _EQ024);
  _EQ024 =  _LC3_B4
         #  _LC7_B4
         # !_LC2_B4 &  second2;

-- Node name is ':635' 
-- Equation name is '_LC6_B5', type is buried 
_LC6_B5  = LCELL( _EQ025);
  _EQ025 = !_LC2_B4 &  second2
         #  _LC8_B4
         #  _LC7_B4;

-- Node name is ':668' 
-- Equation name is '_LC7_B5', type is buried 
_LC7_B5  = LCELL( _EQ026);
  _EQ026 =  _LC6_B5
         # !_LC6_B4 &  second2;

-- Node name is ':701' 
-- Equation name is '_LC2_B5', type is buried 
_LC2_B5  = LCELL( _EQ027);
  _EQ027 =  _LC4_C7
         #  _LC7_B5;

-- Node name is ':734' 
-- Equation name is '_LC2_B3', type is buried 
_LC2_B3  = LCELL( _EQ028);
  _EQ028 =  _LC2_B5
         # !_LC2_B4 & !second2;

-- Node name is ':767' 
-- Equation name is '_LC5_B3', type is buried 
_LC5_B3  = LCELL( _EQ029);
  _EQ029 =  _LC2_B3
         #  _LC1_B4 & !second2;

-- Node name is ':815' 
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = LCELL( _EQ030);
  _EQ030 =  _LC1_B4 &  second2
         #  _LC4_B4 & !second0;

-- Node name is ':821' 
-- Equation name is '_LC3_B5', type is buried 
_LC3_B5  = LCELL( _EQ031);
  _EQ031 =  _LC6_B4 &  _LC8_B4
         #  _LC8_B4 & !second2
         #  _LC4_C7;

-- Node name is ':827' 
-- Equation name is '_LC8_B1', type is buried 
_LC8_B1  = LCELL( _EQ032);
  _EQ032 =  _LC2_B4 &  _LC3_B5
         #  _LC3_B5 &  second2
         #  _LC1_B4 & !second2;

-- Node name is '~859~1' 
-- Equation name is '~859~1', location is LC7_B1, type is buried.
-- synthesized logic cell 
_LC7_B1  = LCELL( _EQ033);
  _EQ033 =  _LC2_B4 &  _LC3_B4
         #  _LC2_B4 &  _LC7_B4
         #  _LC3_B4 & !second2
         #  _LC7_B4 & !second2;

-- Node name is '~865~1' 
-- Equation name is '~865~1', location is LC6_B1, type is buried.
-- synthesized logic cell 
_LC6_B1  = LCELL( _EQ034);
  _EQ034 =  _LC4_B5 & !second2
         # !_LC1_B4 &  _LC4_B5 &  _LC6_B4;

-- Node name is '~871~1' 
-- Equation name is '~871~1', location is LC8_B5, type is buried.
-- synthesized logic cell 
_LC8_B5  = LCELL( _EQ035);
  _EQ035 =  _LC4_B5 &  _LC6_B4
         #  _LC4_B5 & !second2;

-- Node name is '~877~1' 
-- Equation name is '~877~1', location is LC4_B5, type is buried.
-- synthesized logic cell 
_LC4_B5  = LCELL( _EQ036);
  _EQ036 =  _LC1_B3 &  _LC2_B4 & !_LC4_C7
         #  _LC1_B3 & !_LC4_C7 &  second2;

-- Node name is '~883~1' 
-- Equation name is '~883~1', location is LC6_B3, type is buried.
-- synthesized logic cell 
_LC6_B3  = LCELL( _EQ037);
  _EQ037 =  _LC1_B3 &  _LC2_B4
         #  _LC1_B3 &  second2;

-- Node name is '~889~1' 
-- Equation name is '~889~1', location is LC1_B3, type is buried.
-- synthesized logic cell 
_LC1_B3  = LCELL( _EQ038);
  _EQ038 =  _LC1_A3 & !_LC4_B1 &  second2
         #  _LC1_A3 & !_LC1_B4 & !_LC4_B1;



Project Information                                 c:\vhdl\digclock\alert.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,249K