📄 alert.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\vhdl\digclock\alert.rpt
alert
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - B 01 DFFE + 0 3 1 0 :18
- 5 - B 04 DFFE + 1 2 1 0 :20
- 1 - B 01 DFFE + 0 3 1 0 :22
- 3 - B 01 DFFE + 0 3 1 0 :24
- 5 - B 05 DFFE + 0 3 1 0 :26
- 1 - B 05 DFFE + 0 3 1 0 :28
- 8 - B 03 DFFE + 0 3 1 0 :30
- 4 - B 03 DFFE + 0 3 1 0 :32
- 7 - B 03 DFFE + 0 3 1 0 :34
- 3 - B 03 DFFE + 0 3 1 0 :36
- 2 - A 03 OR2 s ! 3 0 0 1 ~155~1
- 3 - A 03 OR2 s ! 2 1 0 1 ~155~2
- 1 - A 03 OR2 ! 3 1 0 11 :155
- 4 - B 04 AND2 s 3 1 0 4 ~397~1
- 7 - B 04 AND2 1 1 0 3 :397
- 3 - B 04 AND2 1 1 0 2 :417
- 1 - C 07 AND2 s ! 4 0 0 5 ~477~1
- 4 - C 07 AND2 2 1 0 3 :497
- 2 - B 04 AND2 s ! 3 1 0 7 ~517~1
- 2 - C 07 AND2 s 2 1 0 1 ~537~1
- 1 - B 04 AND2 s 3 1 0 5 ~537~2
- 6 - B 04 AND2 s ! 3 1 0 5 ~557~1
- 4 - B 01 AND2 1 1 0 4 :557
- 5 - B 01 OR2 1 3 0 1 :602
- 6 - B 05 OR2 1 3 0 2 :635
- 7 - B 05 OR2 1 2 0 2 :668
- 2 - B 05 OR2 0 2 0 2 :701
- 2 - B 03 OR2 1 2 0 2 :734
- 5 - B 03 OR2 1 2 0 2 :767
- 8 - B 04 OR2 2 2 0 2 :815
- 3 - B 05 OR2 1 3 0 1 :821
- 8 - B 01 OR2 1 3 0 1 :827
- 7 - B 01 OR2 s 1 3 0 1 ~859~1
- 6 - B 01 OR2 s 1 3 0 2 ~865~1
- 8 - B 05 OR2 s 1 2 0 1 ~871~1
- 4 - B 05 OR2 s 1 3 0 3 ~877~1
- 6 - B 03 OR2 s 1 2 0 1 ~883~1
- 1 - B 03 OR2 s 1 3 0 3 ~889~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\vhdl\digclock\alert.rpt
alert
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 0/ 48( 0%) 0/ 48( 0%) 8/16( 50%) 0/16( 0%) 0/16( 0%)
B: 7/ 96( 7%) 16/ 48( 33%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 3/ 96( 3%) 0/ 48( 0%) 0/ 48( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\vhdl\digclock\alert.rpt
alert
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clkspk
Device-Specific Information: c:\vhdl\digclock\alert.rpt
alert
** EQUATIONS **
clkspk : INPUT;
minute0 : INPUT;
minute1 : INPUT;
minute2 : INPUT;
minute3 : INPUT;
minute4 : INPUT;
minute5 : INPUT;
minute6 : INPUT;
minute7 : INPUT;
second0 : INPUT;
second1 : INPUT;
second2 : INPUT;
second3 : INPUT;
second4 : INPUT;
second5 : INPUT;
second6 : INPUT;
second7 : INPUT;
-- Node name is 'lamp0'
-- Equation name is 'lamp0', type is output
lamp0 = _LC3_B3;
-- Node name is 'lamp1'
-- Equation name is 'lamp1', type is output
lamp1 = _LC7_B3;
-- Node name is 'lamp2'
-- Equation name is 'lamp2', type is output
lamp2 = _LC4_B3;
-- Node name is 'lamp3'
-- Equation name is 'lamp3', type is output
lamp3 = _LC8_B3;
-- Node name is 'lamp4'
-- Equation name is 'lamp4', type is output
lamp4 = _LC1_B5;
-- Node name is 'lamp5'
-- Equation name is 'lamp5', type is output
lamp5 = _LC5_B5;
-- Node name is 'lamp6'
-- Equation name is 'lamp6', type is output
lamp6 = _LC3_B1;
-- Node name is 'lamp7'
-- Equation name is 'lamp7', type is output
lamp7 = _LC1_B1;
-- Node name is 'lamp8'
-- Equation name is 'lamp8', type is output
lamp8 = _LC5_B4;
-- Node name is 'speak'
-- Equation name is 'speak', type is output
speak = _LC2_B1;
-- Node name is ':18'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE( _EQ001, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ001 = _LC1_A3 & !_LC4_B1 & _LC8_B1
# !_LC1_A3 & _LC2_B1;
-- Node name is ':20'
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = DFFE( _EQ002, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ002 = _LC1_A3 & _LC4_B4 & second0
# !_LC1_A3 & _LC5_B4;
-- Node name is ':22'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( _EQ003, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ003 = _LC6_B1 & _LC7_B1
# !_LC1_A3 & _LC1_B1;
-- Node name is ':24'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = DFFE( _EQ004, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ004 = _LC5_B1 & _LC6_B1
# !_LC1_A3 & _LC3_B1;
-- Node name is ':26'
-- Equation name is '_LC5_B5', type is buried
_LC5_B5 = DFFE( _EQ005, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ005 = _LC6_B5 & _LC8_B5
# !_LC1_A3 & _LC5_B5;
-- Node name is ':28'
-- Equation name is '_LC1_B5', type is buried
_LC1_B5 = DFFE( _EQ006, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ006 = _LC4_B5 & _LC7_B5
# !_LC1_A3 & _LC1_B5;
-- Node name is ':30'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = DFFE( _EQ007, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ007 = _LC2_B5 & _LC6_B3
# !_LC1_A3 & _LC8_B3;
-- Node name is ':32'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ008, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ008 = _LC1_B3 & _LC2_B3
# !_LC1_A3 & _LC4_B3;
-- Node name is ':34'
-- Equation name is '_LC7_B3', type is buried
_LC7_B3 = DFFE( _EQ009, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ009 = _LC1_A3 & !_LC4_B1 & _LC5_B3
# !_LC1_A3 & _LC7_B3;
-- Node name is ':36'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = DFFE( _EQ010, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ010 = _LC1_A3 & _LC4_B1
# _LC1_A3 & _LC5_B3
# !_LC1_A3 & _LC3_B3;
-- Node name is '~155~1'
-- Equation name is '~155~1', location is LC2_A3, type is buried.
-- synthesized logic cell
!_LC2_A3 = _LC2_A3~NOT;
_LC2_A3~NOT = LCELL( _EQ011);
_EQ011 = minute2
# minute1
# !minute0;
-- Node name is '~155~2'
-- Equation name is '~155~2', location is LC3_A3, type is buried.
-- synthesized logic cell
!_LC3_A3 = _LC3_A3~NOT;
_LC3_A3~NOT = LCELL( _EQ012);
_EQ012 = !minute4
# !minute3
# !_LC2_A3;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -