📄 digclock.rpt
字号:
- 5 - C 21 AND2 0 4 0 1 |SELTIME:6|:522
- 4 - C 21 OR2 0 4 0 1 |SELTIME:6|:523
- 6 - C 21 OR2 0 4 0 1 |SELTIME:6|:524
- 7 - C 21 OR2 0 3 0 1 |SELTIME:6|:527
- 8 - C 21 OR2 0 3 0 1 |SELTIME:6|:530
- 2 - C 21 OR2 0 3 0 12 |SELTIME:6|:533
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/144( 0%) 0/ 72( 0%) 5/ 72( 6%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 4/ 72( 5%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 26/144( 18%) 0/ 72( 0%) 36/ 72( 50%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
D: 2/144( 1%) 0/ 72( 0%) 23/ 72( 31%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
E: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 3/144( 2%) 0/ 72( 0%) 0/ 72( 0%) 3/16( 18%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 6/24( 25%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
25: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 10 clkspk
DFF 10 |SECOND:5|:4
INPUT 9 clk
DFF 9 |MINUTE:4|:4
INPUT 3 ckdsp
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 31 reset
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
** EQUATIONS **
ckdsp : INPUT;
clk : INPUT;
clkspk : INPUT;
reset : INPUT;
sethour : INPUT;
setmin : INPUT;
-- Node name is 'daout0'
-- Equation name is 'daout0', type is output
daout0 = _LC2_C31;
-- Node name is 'daout1'
-- Equation name is 'daout1', type is output
daout1 = _LC1_C35;
-- Node name is 'daout2'
-- Equation name is 'daout2', type is output
daout2 = _LC7_C31;
-- Node name is 'daout3'
-- Equation name is 'daout3', type is output
daout3 = _LC5_C31;
-- Node name is 'daout4'
-- Equation name is 'daout4', type is output
daout4 = _LC3_C31;
-- Node name is 'daout5'
-- Equation name is 'daout5', type is output
daout5 = _LC2_C35;
-- Node name is 'daout6'
-- Equation name is 'daout6', type is output
daout6 = _LC7_C35;
-- Node name is 'daout7'
-- Equation name is 'daout7', type is output
daout7 = _LC5_C35;
-- Node name is 'lamp0'
-- Equation name is 'lamp0', type is output
lamp0 = _LC4_D26;
-- Node name is 'lamp1'
-- Equation name is 'lamp1', type is output
lamp1 = _LC6_D26;
-- Node name is 'lamp2'
-- Equation name is 'lamp2', type is output
lamp2 = _LC1_D26;
-- Node name is 'lamp3'
-- Equation name is 'lamp3', type is output
lamp3 = _LC2_D24;
-- Node name is 'lamp4'
-- Equation name is 'lamp4', type is output
lamp4 = _LC3_D21;
-- Node name is 'lamp5'
-- Equation name is 'lamp5', type is output
lamp5 = _LC4_D21;
-- Node name is 'lamp6'
-- Equation name is 'lamp6', type is output
lamp6 = _LC5_D21;
-- Node name is 'lamp7'
-- Equation name is 'lamp7', type is output
lamp7 = _LC5_D20;
-- Node name is 'lamp8'
-- Equation name is 'lamp8', type is output
lamp8 = _LC6_D20;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC8_C33, type is buried.
-- synthesized logic cell
!_LC8_C33 = _LC8_C33~NOT;
_LC8_C33~NOT = LCELL(!reset);
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = _LC1_C33;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = _LC3_C33;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = _LC4_C33;
-- Node name is 'speak'
-- Equation name is 'speak', type is output
speak = _LC6_D24;
-- Node name is '|ALERT:1|:18'
-- Equation name is '_LC6_D24', type is buried
_LC6_D24 = DFFE( _EQ001, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ001 = _LC2_D26 & _LC7_D24
# _LC6_D24 & !_LC8_C36;
-- Node name is '|ALERT:1|:20'
-- Equation name is '_LC6_D20', type is buried
_LC6_D20 = DFFE( _EQ002, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ002 = !_LC3_D20 & _LC6_C20 & _LC8_C36
# _LC6_D20 & !_LC8_C36;
-- Node name is '|ALERT:1|:22'
-- Equation name is '_LC5_D20', type is buried
_LC5_D20 = DFFE( _EQ003, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ003 = _LC1_D21 & _LC7_D20
# _LC5_D20 & !_LC8_C36;
-- Node name is '|ALERT:1|:24'
-- Equation name is '_LC5_D21', type is buried
_LC5_D21 = DFFE( _EQ004, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ004 = _LC1_D21 & _LC8_D20
# _LC5_D21 & !_LC8_C36;
-- Node name is '|ALERT:1|:26'
-- Equation name is '_LC4_D21', type is buried
_LC4_D21 = DFFE( _EQ005, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ005 = _LC6_D21 & _LC8_D21
# _LC4_D21 & !_LC8_C36;
-- Node name is '|ALERT:1|:28'
-- Equation name is '_LC3_D21', type is buried
_LC3_D21 = DFFE( _EQ006, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ006 = _LC2_D21 & _LC7_D21
# _LC3_D21 & !_LC8_C36;
-- Node name is '|ALERT:1|:30'
-- Equation name is '_LC2_D24', type is buried
_LC2_D24 = DFFE( _EQ007, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ007 = _LC4_D24 & _LC8_D24
# _LC2_D24 & !_LC8_C36;
-- Node name is '|ALERT:1|:32'
-- Equation name is '_LC1_D26', type is buried
_LC1_D26 = DFFE( _EQ008, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ008 = _LC3_D24 & _LC8_D26
# _LC1_D26 & !_LC8_C36;
-- Node name is '|ALERT:1|:34'
-- Equation name is '_LC6_D26', type is buried
_LC6_D26 = DFFE( _EQ009, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ009 = _LC2_D26 & _LC5_D26
# _LC6_D26 & !_LC8_C36;
-- Node name is '|ALERT:1|:36'
-- Equation name is '_LC4_D26', type is buried
_LC4_D26 = DFFE( _EQ010, GLOBAL( clkspk), VCC, VCC, VCC);
_EQ010 = _LC5_D26 & _LC8_C36
# _LC7_D26 & _LC8_C36
# _LC4_D26 & !_LC8_C36;
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