📄 digclock.rpt
字号:
C31 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 4/22( 18%)
C32 7/ 8( 87%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 12/22( 54%)
C33 8/ 8(100%) 3/ 8( 37%) 6/ 8( 75%) 1/2 0/2 3/22( 13%)
C35 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 10/22( 45%)
C36 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 1/2 7/22( 31%)
D20 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 7/22( 31%)
D21 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 0/2 8/22( 36%)
D24 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
D26 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 1/2 0/2 6/22( 27%)
D31 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 24/141 ( 17%)
Total logic cells used: 131/1728 ( 7%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.44/4 ( 86%)
Total fan-in: 451/6912 ( 6%)
Total input pins required: 6
Total input I/O cell registers required: 0
Total output pins required: 21
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 131
Total flipflops required: 39
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 19/1728 ( 1%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 8 0 8 0 8 0 8 2 1 8 7 8 0 8 8 98/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 8 0 0 8 0 8 0 0 0 0 1 0 0 0 0 0 33/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 16 16 8 0 16 0 16 0 8 2 1 9 7 8 0 8 8 131/0
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
80 - - - -- INPUT G ^ 0 0 0 0 ckdsp
79 - - - -- INPUT G ^ 0 0 0 0 clk
183 - - - -- INPUT G ^ 0 0 0 0 clkspk
45 - - F -- INPUT ^ 0 0 0 31 reset
46 - - F -- INPUT ^ 0 0 0 1 sethour
47 - - F -- INPUT ^ 0 0 0 1 setmin
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
17 - - C -- OUTPUT 0 1 0 0 daout0
16 - - C -- OUTPUT 0 1 0 0 daout1
15 - - B -- OUTPUT 0 1 0 0 daout2
14 - - B -- OUTPUT 0 1 0 0 daout3
13 - - B -- OUTPUT 0 1 0 0 daout4
12 - - B -- OUTPUT 0 1 0 0 daout5
11 - - A -- OUTPUT 0 1 0 0 daout6
10 - - A -- OUTPUT 0 1 0 0 daout7
19 - - C -- OUTPUT 0 1 0 0 lamp0
24 - - C -- OUTPUT 0 1 0 0 lamp1
25 - - D -- OUTPUT 0 1 0 0 lamp2
26 - - D -- OUTPUT 0 1 0 0 lamp3
27 - - D -- OUTPUT 0 1 0 0 lamp4
28 - - D -- OUTPUT 0 1 0 0 lamp5
29 - - D -- OUTPUT 0 1 0 0 lamp6
30 - - D -- OUTPUT 0 1 0 0 lamp7
31 - - D -- OUTPUT 0 1 0 0 lamp8
7 - - A -- OUTPUT 0 1 0 0 sel0
8 - - A -- OUTPUT 0 1 0 0 sel1
9 - - A -- OUTPUT 0 1 0 0 sel2
68 - - - 24 OUTPUT 0 1 0 0 speak
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: h:\vhdl1\digclock\digclock.rpt
digclock
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - D 24 DFFE + 0 3 1 0 |ALERT:1|:18
- 6 - D 20 DFFE + 0 3 1 0 |ALERT:1|:20
- 5 - D 20 DFFE + 0 3 1 0 |ALERT:1|:22
- 5 - D 21 DFFE + 0 3 1 0 |ALERT:1|:24
- 4 - D 21 DFFE + 0 3 1 0 |ALERT:1|:26
- 3 - D 21 DFFE + 0 3 1 0 |ALERT:1|:28
- 2 - D 24 DFFE + 0 3 1 0 |ALERT:1|:30
- 1 - D 26 DFFE + 0 3 1 0 |ALERT:1|:32
- 6 - D 26 DFFE + 0 3 1 0 |ALERT:1|:34
- 4 - D 26 DFFE + 0 3 1 0 |ALERT:1|:36
- 7 - C 36 OR2 s ! 0 3 0 1 |ALERT:1|~155~1
- 4 - C 28 OR2 s ! 0 3 0 1 |ALERT:1|~155~2
- 8 - C 36 OR2 ! 0 4 0 11 |ALERT:1|:155
- 6 - C 20 AND2 s 0 3 0 4 |ALERT:1|~397~1
- 2 - D 20 AND2 0 3 0 3 |ALERT:1|:417
- 3 - C 22 AND2 s ! 0 4 0 2 |ALERT:1|~437~1
- 7 - C 20 AND2 s ! 0 2 0 4 |ALERT:1|~437~2
- 4 - D 20 AND2 0 4 0 2 |ALERT:1|:437
- 5 - C 20 OR2 ! 0 4 0 3 |ALERT:1|:517
- 1 - D 31 AND2 s ! 0 2 0 4 |ALERT:1|~537~1
- 1 - D 24 AND2 s ! 0 2 0 7 |ALERT:1|~537~2
- 3 - D 20 OR2 s 0 2 0 4 |ALERT:1|~557~1
- 1 - D 20 OR2 s 0 2 0 6 |ALERT:1|~557~2
- 7 - D 26 AND2 0 2 0 1 |ALERT:1|:557
- 8 - D 20 OR2 0 4 0 2 |ALERT:1|:602
- 6 - D 21 OR2 0 3 0 2 |ALERT:1|:635
- 2 - D 21 OR2 0 3 0 2 |ALERT:1|:668
- 8 - D 24 OR2 0 4 0 2 |ALERT:1|:701
- 3 - D 24 OR2 0 2 0 2 |ALERT:1|:734
- 5 - D 26 OR2 0 3 0 2 |ALERT:1|:767
- 5 - D 24 OR2 0 4 0 1 |ALERT:1|:821
- 3 - D 26 OR2 0 4 0 1 |ALERT:1|:823
- 7 - D 24 OR2 0 4 0 1 |ALERT:1|:827
- 1 - D 21 OR2 s 0 4 0 2 |ALERT:1|~859~1
- 7 - D 20 OR2 s 0 4 0 1 |ALERT:1|~859~2
- 8 - D 21 OR2 s 0 3 0 1 |ALERT:1|~871~1
- 7 - D 21 OR2 s 0 4 0 3 |ALERT:1|~877~1
- 4 - D 24 OR2 s 0 4 0 2 |ALERT:1|~883~1
- 8 - D 26 OR2 s 0 3 0 1 |ALERT:1|~889~1
- 2 - D 26 OR2 s 0 3 0 4 |ALERT:1|~895~1
- 1 - C 31 OR2 ! 0 4 0 1 |DELED:2|:402
- 5 - C 35 OR2 0 4 1 0 |DELED:2|:405
- 4 - C 31 OR2 0 4 0 1 |DELED:2|:407
- 7 - C 35 OR2 0 4 1 0 |DELED:2|:438
- 6 - C 31 OR2 s ! 0 4 0 1 |DELED:2|~462~1
- 2 - C 35 OR2 0 4 1 0 |DELED:2|:471
- 3 - C 31 OR2 0 4 1 0 |DELED:2|:504
- 5 - C 31 OR2 0 4 1 0 |DELED:2|:537
- 8 - C 31 OR2 0 4 0 1 |DELED:2|:569
- 7 - C 31 OR2 0 4 1 0 |DELED:2|:570
- 1 - C 35 OR2 0 4 1 0 |DELED:2|:605
- 2 - C 31 AND2 0 4 1 0 |DELED:2|:638
- 2 - C 24 AND2 0 2 0 3 |HOUR:3|LPM_ADD_SUB:103|addcore:adder|:55
- 4 - C 32 OR2 0 3 0 4 |HOUR:3|LPM_ADD_SUB:103|addcore:adder|:69
- 6 - C 26 AND2 0 2 0 1 |HOUR:3|LPM_ADD_SUB:125|addcore:adder|:55
- 5 - C 26 AND2 0 3 0 2 |HOUR:3|LPM_ADD_SUB:125|addcore:adder|:59
- 3 - C 26 DFFE 1 4 0 2 |HOUR:3|da23~118 (|HOUR:3|:71)
- 7 - C 26 DFFE 1 4 0 3 |HOUR:3|da22~118 (|HOUR:3|:72)
- 4 - C 26 DFFE 1 4 0 4 |HOUR:3|da21~118 (|HOUR:3|:73)
- 1 - C 24 DFFE 1 4 0 5 |HOUR:3|da20~118 (|HOUR:3|:74)
- 6 - C 24 DFFE 1 4 0 3 |HOUR:3|da13~116 (|HOUR:3|:75)
- 3 - C 24 DFFE 1 4 0 4 |HOUR:3|da12~116 (|HOUR:3|:76)
- 4 - C 24 DFFE 1 4 0 3 |HOUR:3|da11~116 (|HOUR:3|:77)
- 7 - C 24 DFFE 1 4 0 4 |HOUR:3|da10~116 (|HOUR:3|:78)
- 5 - C 32 OR2 ! 0 2 0 7 |HOUR:3|:106
- 5 - C 24 OR2 ! 0 3 0 3 |HOUR:3|:109
- 8 - C 26 OR2 s 0 4 0 1 |HOUR:3|~182~1
- 2 - C 26 OR2 0 4 0 5 |HOUR:3|:182
- 3 - C 32 OR2 0 4 0 6 |HOUR:3|:200
- 8 - C 24 OR2 ! 0 2 0 1 |HOUR:3|:216
- 5 - C 36 AND2 0 2 0 1 |MINUTE:4|LPM_ADD_SUB:134|addcore:adder|:55
- 2 - C 36 DFFE 2 3 0 8 |MINUTE:4|:4
- 5 - C 28 DFFE 1 4 0 5 |MINUTE:4|da13~153 (|MINUTE:4|:80)
- 7 - C 28 DFFE 1 4 0 4 |MINUTE:4|da12~153 (|MINUTE:4|:81)
- 8 - C 28 DFFE 1 3 0 5 |MINUTE:4|da11~153 (|MINUTE:4|:82)
- 3 - C 28 DFFE 1 2 0 6 |MINUTE:4|da10~153 (|MINUTE:4|:83)
- 1 - C 21 DFFE 1 2 0 3 |MINUTE:4|da23~155 (|MINUTE:4|:84)
- 4 - C 36 DFFE 1 4 0 3 |MINUTE:4|da22~155 (|MINUTE:4|:85)
- 1 - C 36 DFFE 1 4 0 4 |MINUTE:4|da21~155 (|MINUTE:4|:86)
- 6 - C 36 DFFE 1 3 0 5 |MINUTE:4|da20~155 (|MINUTE:4|:87)
- 1 - C 28 OR2 ! 0 4 0 6 |MINUTE:4|:106
- 3 - C 36 OR2 0 4 0 4 |MINUTE:4|:135
- 8 - C 33 SOFT s ! 1 0 0 3 reset~1
- 8 - C 22 AND2 0 2 0 1 |SECOND:5|LPM_ADD_SUB:134|addcore:adder|:55
- 1 - C 22 DFFE + 2 2 0 9 |SECOND:5|:4
- 2 - C 20 DFFE + 1 3 0 7 |SECOND:5|da13~153 (|SECOND:5|:80)
- 8 - C 20 DFFE + 1 3 0 21 |SECOND:5|da12~153 (|SECOND:5|:81)
- 3 - C 20 DFFE + 1 2 0 13 |SECOND:5|da11~153 (|SECOND:5|:82)
- 4 - C 20 DFFE + 1 3 0 10 |SECOND:5|da10~153 (|SECOND:5|:83)
- 4 - C 22 DFFE + 1 1 0 3 |SECOND:5|da23~155 (|SECOND:5|:84)
- 5 - C 22 DFFE + 1 3 0 3 |SECOND:5|da22~155 (|SECOND:5|:85)
- 2 - C 22 DFFE + 1 3 0 4 |SECOND:5|da21~155 (|SECOND:5|:86)
- 6 - C 22 DFFE + 1 2 0 5 |SECOND:5|da20~155 (|SECOND:5|:87)
- 1 - C 20 OR2 ! 0 4 0 5 |SECOND:5|:106
- 7 - C 22 OR2 ! 0 4 0 4 |SECOND:5|:135
- 4 - C 33 DFFE + 0 3 1 13 |SELTIME:6|count2 (|SELTIME:6|:34)
- 3 - C 33 DFFE + 0 2 1 14 |SELTIME:6|count1 (|SELTIME:6|:35)
- 1 - C 33 DFFE + 0 1 1 15 |SELTIME:6|count0 (|SELTIME:6|:36)
- 2 - C 33 AND2 0 3 0 4 |SELTIME:6|:417
- 1 - C 30 OR2 1 3 0 1 |SELTIME:6|:420
- 2 - C 32 AND2 0 4 0 1 |SELTIME:6|:431
- 1 - C 32 OR2 0 4 0 1 |SELTIME:6|:432
- 4 - C 19 AND2 0 3 0 4 |SELTIME:6|:437
- 7 - C 32 OR2 0 4 0 1 |SELTIME:6|:440
- 3 - C 19 AND2 0 3 0 4 |SELTIME:6|:447
- 6 - C 32 OR2 0 3 0 1 |SELTIME:6|:450
- 5 - C 19 AND2 0 3 0 4 |SELTIME:6|:457
- 2 - C 29 OR2 0 3 0 1 |SELTIME:6|:460
- 5 - C 33 AND2 0 3 0 4 |SELTIME:6|:467
- 1 - C 29 OR2 0 3 0 12 |SELTIME:6|:470
- 1 - C 26 OR2 1 3 0 1 |SELTIME:6|:476
- 8 - C 19 AND2 0 4 0 1 |SELTIME:6|:480
- 7 - C 19 OR2 0 4 0 1 |SELTIME:6|:481
- 1 - C 19 OR2 0 4 0 1 |SELTIME:6|:482
- 2 - C 28 OR2 0 3 0 1 |SELTIME:6|:485
- 6 - C 35 OR2 0 3 0 1 |SELTIME:6|:488
- 4 - C 35 OR2 0 3 0 12 |SELTIME:6|:491
- 7 - C 33 OR2 1 3 0 1 |SELTIME:6|:497
- 6 - C 19 AND2 0 4 0 1 |SELTIME:6|:501
- 6 - C 33 OR2 0 4 0 1 |SELTIME:6|:502
- 2 - C 19 OR2 0 4 0 1 |SELTIME:6|:503
- 6 - C 28 OR2 0 3 0 1 |SELTIME:6|:506
- 3 - C 35 OR2 0 3 0 1 |SELTIME:6|:509
- 8 - C 35 OR2 0 3 0 12 |SELTIME:6|:512
- 3 - C 21 OR2 1 3 0 1 |SELTIME:6|:518
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