📄 seltime.rpt
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Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: c:\vhdl\digclock\seltime.rpt
seltime
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - A -- OUTPUT 0 1 0 0 daout0
87 - - - 12 OUTPUT 0 1 0 0 daout1
46 - - - 10 OUTPUT 0 1 0 0 daout2
50 - - - 02 OUTPUT 0 1 0 0 daout3
71 - - A -- OUTPUT 0 1 0 0 sel0
70 - - A -- OUTPUT 0 1 0 0 sel1
68 - - A -- OUTPUT 0 1 0 0 sel2
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: c:\vhdl\digclock\seltime.rpt
seltime
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 09 DFFE + 1 2 1 13 count2 (:34)
- 3 - A 09 DFFE + 1 1 1 14 count1 (:35)
- 1 - A 09 DFFE + 1 0 1 15 count0 (:36)
- 6 - A 09 AND2 0 3 0 4 :417
- 3 - A 01 OR2 2 2 0 1 :420
- 5 - A 01 AND2 1 3 0 1 :431
- 4 - A 01 OR2 0 4 0 1 :432
- 1 - A 10 AND2 0 3 0 4 :437
- 6 - A 01 OR2 1 3 0 1 :440
- 1 - A 11 AND2 0 3 0 4 :447
- 7 - A 01 OR2 1 2 0 1 :450
- 1 - A 01 AND2 0 3 0 4 :457
- 8 - A 01 OR2 1 2 0 1 :460
- 2 - A 09 AND2 0 3 0 4 :467
- 2 - A 01 OR2 1 2 1 1 :470
- 2 - A 10 OR2 2 2 0 1 :476
- 4 - A 10 AND2 1 3 0 1 :480
- 3 - A 10 OR2 0 4 0 1 :481
- 5 - A 10 OR2 1 3 0 1 :482
- 6 - A 10 OR2 1 2 0 1 :485
- 8 - A 10 OR2 1 2 0 1 :488
- 7 - A 10 OR2 1 2 1 1 :491
- 3 - A 11 OR2 2 2 0 1 :497
- 5 - A 11 AND2 1 3 0 1 :501
- 4 - A 11 OR2 0 4 0 1 :502
- 6 - A 11 OR2 1 3 0 1 :503
- 7 - A 11 OR2 1 2 0 1 :506
- 8 - A 11 OR2 1 2 0 1 :509
- 2 - A 11 OR2 1 2 1 1 :512
- 8 - A 09 OR2 2 2 0 1 :518
- 4 - A 09 AND2 1 3 0 1 :522
- 5 - A 09 OR2 0 4 0 1 :523
- 1 - A 08 OR2 1 3 0 1 :524
- 2 - A 08 OR2 1 2 0 1 :527
- 3 - A 08 OR2 1 2 0 1 :530
- 8 - A 08 OR2 1 2 1 1 :533
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: c:\vhdl\digclock\seltime.rpt
seltime
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 11/ 96( 11%) 20/ 48( 41%) 0/ 48( 0%) 6/16( 37%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 2/24( 8%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: c:\vhdl\digclock\seltime.rpt
seltime
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 ckdsp
Device-Specific Information: c:\vhdl\digclock\seltime.rpt
seltime
** EQUATIONS **
ckdsp : INPUT;
hour0 : INPUT;
hour1 : INPUT;
hour2 : INPUT;
hour3 : INPUT;
hour4 : INPUT;
hour5 : INPUT;
hour6 : INPUT;
hour7 : INPUT;
minute0 : INPUT;
minute1 : INPUT;
minute2 : INPUT;
minute3 : INPUT;
minute4 : INPUT;
minute5 : INPUT;
minute6 : INPUT;
minute7 : INPUT;
reset : INPUT;
second0 : INPUT;
second1 : INPUT;
second2 : INPUT;
second3 : INPUT;
second4 : INPUT;
second5 : INPUT;
second6 : INPUT;
second7 : INPUT;
-- Node name is ':36' = 'count0'
-- Equation name is 'count0', location is LC1_A9, type is buried.
count0 = DFFE(!count0, GLOBAL( ckdsp), VCC, VCC, reset);
-- Node name is ':35' = 'count1'
-- Equation name is 'count1', location is LC3_A9, type is buried.
count1 = DFFE( _EQ001, GLOBAL( ckdsp), VCC, VCC, reset);
_EQ001 = !count0 & count1
# count0 & !count1;
-- Node name is ':34' = 'count2'
-- Equation name is 'count2', location is LC7_A9, type is buried.
count2 = DFFE( _EQ002, GLOBAL( ckdsp), VCC, VCC, reset);
_EQ002 = count0 & count1 & !count2
# !count1 & count2
# !count0 & count2;
-- Node name is 'daout0'
-- Equation name is 'daout0', type is output
daout0 = _LC8_A8;
-- Node name is 'daout1'
-- Equation name is 'daout1', type is output
daout1 = _LC2_A11;
-- Node name is 'daout2'
-- Equation name is 'daout2', type is output
daout2 = _LC7_A10;
-- Node name is 'daout3'
-- Equation name is 'daout3', type is output
daout3 = _LC2_A1;
-- Node name is 'sel0'
-- Equation name is 'sel0', type is output
sel0 = count0;
-- Node name is 'sel1'
-- Equation name is 'sel1', type is output
sel1 = count1;
-- Node name is 'sel2'
-- Equation name is 'sel2', type is output
sel2 = count2;
-- Node name is ':417'
-- Equation name is '_LC6_A9', type is buried
_LC6_A9 = LCELL( _EQ003);
_EQ003 = count0 & !count1 & count2;
-- Node name is ':420'
-- Equation name is '_LC3_A1', type is buried
_LC3_A1 = LCELL( _EQ004);
_EQ004 = _LC2_A1 & !_LC6_A9 & reset
# hour7 & _LC6_A9;
-- Node name is ':431'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ005);
_EQ005 = !count0 & !count1 & count2 & hour3;
-- Node name is ':432'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = LCELL( _EQ006);
_EQ006 = count1 & _LC3_A1
# count0 & _LC3_A1
# !count2 & _LC3_A1;
-- Node name is ':437'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ007);
_EQ007 = count0 & count1 & !count2;
-- Node name is ':440'
-- Equation name is '_LC6_A1', type is buried
_LC6_A1 = LCELL( _EQ008);
_EQ008 = !_LC1_A10 & _LC4_A1
# !_LC1_A10 & _LC5_A1
# _LC1_A10 & minute7;
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