fenpin.tan.qmsg

分频器 8分频器 50 已经测试 可以用 代码可更改

{ "Info" "ITDB_FULL_MIN_TCO_RESULT" "clk clout clout~reg0 8.000 ns register " "Info: Minimum tco from clock clk to destination pin clout through register clout~reg0 is 8.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.000 ns + Shortest register " "Info: + Shortest clock path from clock clk to source register is 3.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk 1 CLK PIN_83 4 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'" {  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clk } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 5 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 3.000 ns clout~reg0 2 REG LC3 1 " "Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" {  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "0.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 100.00 % " "Info: Total cell delay = 3.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns + " "Info: + Micro clock to output delay of source is 1.000 ns" {  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Shortest register pin " "Info: + Shortest register to pin delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clout~reg0 1 REG LC3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'" {  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "" { clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.000 ns) 4.000 ns clout 2 PIN PIN_12 0 " "Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'clout'" {  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "4.000 ns" { clout~reg0 clout } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 6 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 100.00 % " "Info: Total cell delay = 4.000 ns ( 100.00 % )" {  } {  } 0}  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "4.000 ns" { clout~reg0 clout } "NODE_NAME" } } }  } 0}  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "3.000 ns" { clk clout~reg0 } "NODE_NAME" } } } { "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" "" "" { Report "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin_cmp.qrpt" Compiler "fenpin" "UNKNOWN" "V1" "G:/Program Files/quartus/altera/work/实验三/fenpin/db/fenpin.quartus_db" { Floorplan "" "" "4.000 ns" { clout~reg0 clout } "NODE_NAME" } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 10 15:44:46 2009 " "Info: Processing ended: Sun May 10 15:44:46 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}