fenpin.map.qmsg

分频器 8分频器 50 已经测试 可以用 代码可更改

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 10 15:44:41 2009 " "Info: Processing started: Sun May 10 15:44:41 2009" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off fenpin -c fenpin " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fenpin -c fenpin" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fenpin.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file fenpin.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fenpin-code " "Info: Found design unit 1: fenpin-code" {  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "fenpin-code" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 8 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 fenpin " "Info: Found entity 1: fenpin" {  } { { "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" "fenpin" "" { Text "G:/Program Files/quartus/altera/work/实验三/fenpin/fenpin.vhd" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "clk " "Info: Promoted clock signal driven by pin clk to global clock signal" {  } {  } 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "clr " "Info: Promoted clear signal driven by pin clr to global clear signal" {  } {  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "7 " "Info: Implemented 7 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "4 " "Info: Implemented 4 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Sun May 10 15:44:42 2009 " "Info: Processing ended: Sun May 10 15:44:42 2009" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" {  } {  } 0}  } {  } 0}