fenpin.vhd

分频器 8分频器 50 已经测试 可以用 代码可更改

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity fenpin is
port(clk,clr : in STD_LOGIC;
     clout : out STD_LOGIC);
end fenpin;
architecture code of fenpin is
  signal tmp:integer range 0 to 7;
begin 
  p1:process(clr,clk)
  begin
    if clr='0' then
     tmp<=0;
    else if(clk 'event and clk='1') then
      if tmp=7 then
         tmp<=0;
      else 
         tmp<=tmp+1;
      end if;
      if tmp<4 then
         clout<='0';
      else 
         clout<='1';
      end if;
     end if;
 end if;
end process p1;  
end code;