fenpin.tan.rpt

分频器 8分频器 50 已经测试 可以用 代码可更改

; Slack ; Required tsu ; Actual tsu ; From ; To         ; To Clock ;
+-------+--------------+------------+------+------------+----------+
; N/A   ; None         ; 11.000 ns  ; clr  ; clout~reg0 ; clk      ;
+-------+--------------+------------+------+------------+----------+


+---------------------------------------------------------------------+
; tco                                                                 ;
+-------+--------------+------------+------------+-------+------------+
; Slack ; Required tco ; Actual tco ; From       ; To    ; From Clock ;
+-------+--------------+------------+------------+-------+------------+
; N/A   ; None         ; 8.000 ns   ; clout~reg0 ; clout ; clk        ;
+-------+--------------+------------+------------+-------+------------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+------+------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To         ; To Clock ;
+---------------+-------------+-----------+------+------------+----------+
; N/A           ; None        ; -3.000 ns ; clr  ; clout~reg0 ; clk      ;
+---------------+-------------+-----------+------+------------+----------+


+-------------------------------------------------------------------------------------+
; Minimum tco                                                                         ;
+---------------+------------------+----------------+------------+-------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From       ; To    ; From Clock ;
+---------------+------------------+----------------+------------+-------+------------+
; N/A           ; None             ; 8.000 ns       ; clout~reg0 ; clout ; clk        ;
+---------------+------------------+----------------+------------+-------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Sun May 10 15:44:46 2009
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off fenpin -c fenpin
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node clk is an undefined clock
Info: Clock clk has Internal fmax of 76.92 MHz between source register tmp[2] and destination register clout~reg0 (period= 13.0 ns)
    Info: + Longest register to register delay is 8.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'tmp[2]'
        Info: 2: + IC(2.000 ns) + CELL(6.000 ns) = 8.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: Total cell delay = 6.000 ns ( 75.00 % )
        Info: Total interconnect delay = 2.000 ns ( 25.00 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock clk to destination register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
        Info: - Longest clock path from clock clk to source register is 3.000 ns
            Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
            Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC4; Fanout = 2; REG Node = 'tmp[2]'
            Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Micro setup delay of destination is 4.000 ns
Info: tsu for register clout~reg0 (data pin = clr, clock pin = clk) is 11.000 ns
    Info: + Longest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 4; PIN Node = 'clr'
        Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: Total cell delay = 9.000 ns ( 90.00 % )
        Info: Total interconnect delay = 1.000 ns ( 10.00 % )
    Info: + Micro setup delay of destination is 4.000 ns
    Info: - Shortest clock path from clock clk to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
Info: tco from clock clk to destination pin clout through register clout~reg0 is 8.000 ns
    Info: + Longest clock path from clock clk to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Longest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'clout'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: th for register clout~reg0 (data pin = clr, clock pin = clk) is -3.000 ns
    Info: + Longest clock path from clock clk to destination register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro hold delay of destination is 4.000 ns
    Info: - Shortest pin to register delay is 10.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_1; Fanout = 4; PIN Node = 'clr'
        Info: 2: + IC(1.000 ns) + CELL(6.000 ns) = 10.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: Total cell delay = 9.000 ns ( 90.00 % )
        Info: Total interconnect delay = 1.000 ns ( 10.00 % )
Info: Minimum tco from clock clk to destination pin clout through register clout~reg0 is 8.000 ns
    Info: + Shortest clock path from clock clk to source register is 3.000 ns
        Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 4; CLK Node = 'clk'
        Info: 2: + IC(0.000 ns) + CELL(0.000 ns) = 3.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: Total cell delay = 3.000 ns ( 100.00 % )
    Info: + Micro clock to output delay of source is 1.000 ns
    Info: + Shortest register to pin delay is 4.000 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 1; REG Node = 'clout~reg0'
        Info: 2: + IC(0.000 ns) + CELL(4.000 ns) = 4.000 ns; Loc. = PIN_12; Fanout = 0; PIN Node = 'clout'
        Info: Total cell delay = 4.000 ns ( 100.00 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun May 10 15:44:46 2009
    Info: Elapsed time: 00:00:00