ncofsymbol_tb.v

quartus2环境中设计的高速任意波形发生器

//	Copyright (C) 1988-2007 Altera Corporation

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//	support information, device programming or simulation file, and any other
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//	program PLD devices (but not masked PLD devices) from Altera.  Any other
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//   NCO ver 7.2 VERILOG HDL TESTBENCH
`timescale 1ps / 1ps
module ncofsymbol_tb;
wire [9:0] sin_val;
reg [31:0] phi;
reg [15:0] pmod;
wire out_valid;
reg reset_n;
wire reset; 
assign reset = !reset_n;
reg clken;
reg clk;

initial
  begin
    $dumpvars;
    #0 clk = 1'b0;
    #0 reset_n = 1'b0;
    #0 clken = 1'b1;
    #0 phi = 32'b00001010001111010111000010100100;
    #0 pmod = 4096;
    #27999 reset_n = 1'b1;
  end

always
  begin
    #2000 clk = 1;
    #2000 clk = 0;
  end

integer sin_ch, sin_print;
initial
  begin
    sin_ch = $fopen ("fsin_o_ver_ncofsymbol.txt");
  end

always @(posedge clk)
  begin
    if(reset_n==1'b1 & out_valid==1'b1)
      begin
        if (sin_val[9:0] < (1<<9))
          sin_print = sin_val[9:0];
        else
          sin_print =  sin_val[9:0] - (1<<10);

    $fdisplay (sin_ch, "%d", sin_print);
      end
end

ncofsymbol i_ncofsymbol (
    .out_valid(out_valid),
    .fsin_o(sin_val[9:0]),
    .phi_inc_i(phi[31:0]),
    .phase_mod_i(pmod),
    .reset_n(reset_n),
    .clken(clken),
    .clk(clk)
    );

endmodule